2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/immap_85xx.h>
12 #include <asm/processor.h>
13 #include <asm/fsl_ddr_sdram.h>
14 #include <asm/fsl_ddr_dimm_params.h>
16 #include <asm/fsl_law.h>
18 #ifdef CONFIG_SYS_DDR_RAW_TIMING
19 #if defined(CONFIG_P1020RDB_PROTO) || \
20 defined(CONFIG_P1021RDB) || \
21 defined(CONFIG_P1020UTM)
22 /* Micron MT41J256M8_187E */
23 dimm_params_t ddr_raw_timing = {
25 .rank_density = 1073741824u,
26 .capacity = 1073741824u,
27 .primary_sdram_width = 32,
33 .n_banks_per_sdram_device = 8,
35 .burst_lengths_bitmask = 0x0c,
38 .caslat_X = 0x1e << 4, /* 5,6,7,8 */
49 .refresh_rate_ps = 7800000,
52 #elif defined(CONFIG_P2020RDB)
53 /* Micron MT41J128M16_15E */
54 dimm_params_t ddr_raw_timing = {
56 .rank_density = 1073741824u,
57 .capacity = 1073741824u,
58 .primary_sdram_width = 64,
64 .n_banks_per_sdram_device = 8,
66 .burst_lengths_bitmask = 0x0c,
69 .caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */
80 .refresh_rate_ps = 7800000,
83 #elif defined(CONFIG_P1020MBG)
84 /* Micron MT41J512M8_187E */
85 dimm_params_t ddr_raw_timing = {
87 .rank_density = 1073741824u,
88 .capacity = 2147483648u,
89 .primary_sdram_width = 32,
95 .n_banks_per_sdram_device = 8,
97 .burst_lengths_bitmask = 0x0c,
100 .caslat_X = 0x1e << 4, /* 5,6,7,8 */
111 .refresh_rate_ps = 7800000,
114 #elif defined(CONFIG_P1020RDB)
116 * Samsung K4B2G0846C-HCF8
117 * The following timing are for "downshift"
118 * i.e. to use CL9 part as CL7
119 * otherwise, tAA, tRCD, tRP will be 13500ps
120 * and tRC will be 49500ps
122 dimm_params_t ddr_raw_timing = {
124 .rank_density = 1073741824u,
125 .capacity = 1073741824u,
126 .primary_sdram_width = 32,
128 .registered_dimm = 0,
132 .n_banks_per_sdram_device = 8,
134 .burst_lengths_bitmask = 0x0c,
137 .caslat_X = 0x1e << 4, /* 5,6,7,8 */
148 .refresh_rate_ps = 7800000,
151 #elif defined(CONFIG_P1024RDB) || \
152 defined(CONFIG_P1025RDB)
154 * Samsung K4B2G0846C-HCH9
155 * The following timing are for "downshift"
156 * i.e. to use CL9 part as CL7
157 * otherwise, tAA, tRCD, tRP will be 13500ps
158 * and tRC will be 49500ps
160 dimm_params_t ddr_raw_timing = {
162 .rank_density = 1073741824u,
163 .capacity = 1073741824u,
164 .primary_sdram_width = 32,
166 .registered_dimm = 0,
170 .n_banks_per_sdram_device = 8,
172 .burst_lengths_bitmask = 0x0c,
175 .caslat_X = 0x3e << 4, /* 5,6,7,8,9 */
186 .refresh_rate_ps = 7800000,
190 #error Missing raw timing data for this board
193 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
194 unsigned int controller_number,
195 unsigned int dimm_number)
197 const char dimm_model[] = "Fixed DDR on board";
199 if ((controller_number == 0) && (dimm_number == 0)) {
200 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
201 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
202 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
207 #endif /* CONFIG_SYS_DDR_RAW_TIMING */
209 #ifdef CONFIG_SYS_DDR_CS0_BNDS
210 /* Fixed sdram init -- doesn't use serial presence detect. */
211 phys_size_t fixed_sdram(void)
216 fsl_ddr_cfg_regs_t ddr_cfg_regs = {
217 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
218 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
219 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
220 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
221 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
222 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
223 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
225 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
226 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
227 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
228 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
229 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
230 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
231 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
232 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
233 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
234 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
235 .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
236 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
237 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
238 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
239 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
240 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
241 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
242 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
243 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
244 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
245 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
248 get_sys_info(&sysinfo);
249 printf("Configuring DDR for %s MT/s data rate\n",
250 strmhz(buf, sysinfo.freqDDRBus));
252 ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
254 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
256 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
257 ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
258 printf("ERROR setting Local Access Windows for DDR\n");
266 void fsl_ddr_board_options(memctl_options_t *popts,
267 dimm_params_t *pdimm,
268 unsigned int ctrl_num)
271 popts->clk_adjust = 6;
272 popts->cpo_override = 0x1f;
273 popts->write_data_delay = 2;
274 popts->half_strength_driver_enable = 1;
275 /* Write leveling override */
277 popts->wrlvl_override = 1;
278 popts->wrlvl_sample = 0xf;
279 popts->wrlvl_start = 0x8;
280 popts->trwt_override = 1;
283 if (pdimm->primary_sdram_width == 64)
284 popts->data_bus_width = 0;
285 else if (pdimm->primary_sdram_width == 32)
286 popts->data_bus_width = 1;
288 printf("Error in DDR bus width configuration!\n");
290 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
291 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
292 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;