1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010-2012 Freescale Semiconductor, Inc.
4 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5 * Timur Tabi <timur@freescale.com>
16 #include <asm/processor.h>
18 #include <asm/cache.h>
19 #include <asm/immap_85xx.h>
20 #include <asm/fsl_pci.h>
21 #include <fsl_ddr_sdram.h>
22 #include <asm/fsl_serdes.h>
24 #include <linux/libfdt.h>
25 #include <fdt_support.h>
28 #include <asm/fsl_law.h>
33 #include "../common/ngpixis.h"
35 int board_early_init_f(void)
37 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
39 /* Set pmuxcr to allow both i2c1 and i2c2 */
40 setbits_be32(&gur->pmuxcr, 0x1000);
41 #ifdef CONFIG_SYS_RAMBOOT
42 setbits_be32(&gur->pmuxcr,
43 in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
46 /* Read back the register to synchronize the write. */
47 in_be32(&gur->pmuxcr);
49 /* Set the pin muxing to enable ETSEC2. */
50 clrbits_be32(&gur->pmuxcr2, 0x001F8000);
53 clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
62 printf("Board: P1022DS Sys ID: 0x%02x, "
63 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
64 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
66 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
68 switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
70 printf ("vBank: %u\n", ((sw & 0x30) >> 4));
84 #define CONFIG_TFP410_I2C_ADDR 0x38
86 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
87 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
88 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
90 /* Route the I2C1 pins to the SSI port instead. */
91 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
93 /* Choose the 12.288Mhz codec reference clock */
94 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
96 /* Choose the 11.2896Mhz codec reference clock */
97 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
100 #define CONFIG_PIXIS_BRDCFG0_USB2 0x10
101 /* Connect to TFM bus */
102 #define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
104 #define CONFIG_PIXIS_BRDCFG0_SPI 0x80
106 int misc_init_r(void)
111 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
113 /* For DVI, enable the TFP410 Encoder. */
116 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
118 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
120 debug("DVI Encoder Read: 0x%02x\n", temp);
123 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
125 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
127 debug("DVI Encoder Read: 0x%02x\n",temp);
129 /* Enable the USB2 in PMUXCR2 and FGPA */
130 if (hwconfig("usb2")) {
131 clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
132 MPC85xx_PMUXCR2_USB);
133 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
136 /* tdm and audio can not enable simultaneous*/
137 if (hwconfig("tdm") && hwconfig("audclk")){
138 printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
142 /* Enable the TDM in PMUXCR and FGPA */
143 if (hwconfig("tdm")) {
144 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
146 setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
147 /* TDM need some configration option by SPI */
148 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
150 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
154 * Enable the reference clock for the WM8776 codec, and route the MUX
155 * pins for SSI. The default is the 12.288 MHz clock
158 if (hwconfig("audclk")) {
159 temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
160 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
161 temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
163 audclk = hwconfig_arg("audclk", &arglen);
164 /* Check the first two chars only */
165 if (audclk && (strncmp(audclk, "11", 2) == 0))
166 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
168 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
169 setbits_8(&pixis->brdcfg1, temp);
176 * A list of PCI and SATA slots
189 * This array maps the slot identifiers to their names on the P1022DS board.
191 static const char *slot_names[] = {
192 [SLOT_PCIE1] = "Slot 1",
193 [SLOT_PCIE2] = "Slot 2",
194 [SLOT_PCIE3] = "Slot 3",
195 [SLOT_PCIE4] = "Slot 4",
196 [SLOT_PCIE5] = "Mini-PCIe",
197 [SLOT_SATA1] = "SATA 1",
198 [SLOT_SATA2] = "SATA 2",
202 * This array maps a given SERDES configuration and SERDES device to the PCI or
203 * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
205 static u8 serdes_dev_slot[][SATA2 + 1] = {
206 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
207 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
208 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
209 [PCIE2] = SLOT_PCIE5 },
210 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
211 [PCIE2] = SLOT_PCIE3,
212 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
213 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
214 [PCIE2] = SLOT_PCIE3 },
215 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
216 [PCIE2] = SLOT_PCIE3,
217 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
218 [0x1c] = { [PCIE1] = SLOT_PCIE1,
219 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
220 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
221 [0x1f] = { [PCIE1] = SLOT_PCIE1 },
226 * Returns the name of the slot to which the PCIe or SATA controller is
229 const char *board_serdes_name(enum srds_prtcl device)
231 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
232 u32 pordevsr = in_be32(&gur->pordevsr);
233 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
234 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
235 enum slot_id slot = serdes_dev_slot[srds_cfg][device];
236 const char *name = slot_names[slot];
245 void pci_init_board(void)
247 fsl_pcie_init_board(0);
251 int board_early_init_r(void)
253 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
254 int flash_esel = find_tlb_idx((void *)flashbase, 1);
257 * Remap Boot flash + PROMJET region to caching-inhibited
258 * so that flash can be erased properly.
261 /* Flush d-cache and invalidate i-cache of any FLASH data */
265 if (flash_esel == -1) {
266 /* very unlikely unless something is messed up */
267 puts("Error: Could not find TLB for FLASH BASE\n");
268 flash_esel = 2; /* give our best effort to continue */
270 /* invalidate existing TLB entry for flash + promjet */
271 disable_tlb(flash_esel);
274 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
275 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
276 0, flash_esel, BOOKE_PAGESZ_256M, 1);
282 * Initialize on-board and/or PCI Ethernet devices
286 * 0, no ethernet devices found
287 * >0, number of ethernet devices initialized
289 int board_eth_init(bd_t *bis)
291 struct fsl_pq_mdio_info mdio_info;
292 struct tsec_info_struct tsec_info[2];
293 unsigned int num = 0;
296 SET_STD_TSEC_INFO(tsec_info[num], 1);
300 SET_STD_TSEC_INFO(tsec_info[num], 2);
304 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
305 mdio_info.name = DEFAULT_MII_NAME;
306 fsl_pq_mdio_init(bis, &mdio_info);
308 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
311 #ifdef CONFIG_OF_BOARD_SETUP
313 * ft_codec_setup - fix up the clock-frequency property of the codec node
315 * Update the clock-frequency property based on the value of the 'audclk'
316 * hwconfig option. If audclk is not specified, then don't write anything
317 * to the device tree, because it means that the codec clock is disabled.
319 static void ft_codec_setup(void *blob, const char *compatible)
325 audclk = hwconfig_arg("audclk", &arglen);
327 if (strncmp(audclk, "11", 2) == 0)
332 do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
337 int ft_board_setup(void *blob, bd_t *bd)
342 ft_cpu_setup(blob, bd);
344 base = env_get_bootm_low();
345 size = env_get_bootm_size();
347 fdt_fixup_memory(blob, (u64)base, (u64)size);
349 #ifdef CONFIG_HAS_FSL_DR_USB
350 fsl_fdt_fixup_dr_usb(blob, bd);
355 #ifdef CONFIG_FSL_SGMII_RISER
356 fsl_sgmii_riser_fdt_fixup(blob);
359 /* Update the WM8776 node's clock frequency property */
360 ft_codec_setup(blob, "wlf,wm8776");