2 * Copyright 2010 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
15 #include <asm/processor.h>
17 #include <asm/cache.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_pci.h>
20 #include <asm/fsl_ddr_sdram.h>
21 #include <asm/fsl_serdes.h>
24 #include <fdt_support.h>
26 #include <asm/fsl_law.h>
31 #include "../common/ngpixis.h"
33 DECLARE_GLOBAL_DATA_PTR;
35 int board_early_init_f(void)
37 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
39 /* Set pmuxcr to allow both i2c1 and i2c2 */
40 setbits_be32(&gur->pmuxcr, 0x1000);
42 /* Read back the register to synchronize the write. */
43 in_be32(&gur->pmuxcr);
45 /* Set the pin muxing to enable ETSEC2. */
46 clrbits_be32(&gur->pmuxcr2, 0x001F8000);
55 puts("Board: P1022DS ");
57 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
58 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
60 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
62 switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
64 printf ("vBank: %u\n", ((sw & 0x30) >> 4));
78 phys_size_t initdram(int board_type)
80 phys_size_t dram_size = 0;
82 puts("Initializing....\n");
84 dram_size = fsl_ddr_sdram();
85 dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;
91 #define CONFIG_TFP410_I2C_ADDR 0x38
97 /* Enable the TFP410 Encoder */
100 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
103 /* Verify if enabled */
105 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
108 debug("DVI Encoder Read: 0x%02x\n", temp);
111 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
114 /* Verify if enabled */
116 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
119 debug("DVI Encoder Read: 0x%02x\n",temp);
124 static void configure_pcie(struct fsl_pci_info *info,
125 struct pci_controller *hose,
126 const char *connected)
128 static int bus_number = 0;
131 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
132 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
133 is_endpoint = fsl_setup_hose(hose, info->regs);
134 printf(" PCIE%u connected to %s as %s (base addr %lx)\n",
135 info->pci_num, connected,
136 is_endpoint ? "Endpoint" : "Root Complex", info->regs);
137 bus_number = fsl_pci_init_port(info, hose, bus_number);
141 static struct pci_controller pcie1_hose;
145 static struct pci_controller pcie2_hose;
149 static struct pci_controller pcie3_hose;
153 void pci_init_board(void)
155 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
156 struct fsl_pci_info pci_info;
157 u32 devdisr = in_be32(&gur->devdisr);
160 if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
161 SET_STD_PCIE_INFO(pci_info, 1);
162 configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
164 printf(" PCIE1: disabled\n");
167 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
171 if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
172 SET_STD_PCIE_INFO(pci_info, 2);
173 configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
175 printf(" PCIE2: disabled\n");
178 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
182 if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
183 SET_STD_PCIE_INFO(pci_info, 3);
184 configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
186 printf(" PCIE3: disabled\n");
189 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
194 int board_early_init_r(void)
196 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
197 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
200 * Remap Boot flash + PROMJET region to caching-inhibited
201 * so that flash can be erased properly.
204 /* Flush d-cache and invalidate i-cache of any FLASH data */
208 /* invalidate existing TLB entry for flash + promjet */
209 disable_tlb(flash_esel);
211 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
212 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
213 0, flash_esel, BOOKE_PAGESZ_256M, 1);
219 * Initialize on-board and/or PCI Ethernet devices
223 * 0, no ethernet devices found
224 * >0, number of ethernet devices initialized
226 int board_eth_init(bd_t *bis)
228 struct tsec_info_struct tsec_info[2];
229 unsigned int num = 0;
232 SET_STD_TSEC_INFO(tsec_info[num], 1);
236 SET_STD_TSEC_INFO(tsec_info[num], 2);
240 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
243 #ifdef CONFIG_OF_BOARD_SETUP
244 void ft_board_setup(void *blob, bd_t *bd)
249 ft_cpu_setup(blob, bd);
251 base = getenv_bootm_low();
252 size = getenv_bootm_size();
254 fdt_fixup_memory(blob, (u64)base, (u64)size);
257 ft_fsl_pci_setup(blob, "pci0", &pcie1_hose);
259 ft_fsl_pci_setup(blob, "pci0", NULL);
263 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
265 ft_fsl_pci_setup(blob, "pci1", NULL);
269 ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
271 ft_fsl_pci_setup(blob, "pci2", NULL);
274 #ifdef CONFIG_FSL_SGMII_RISER
275 fsl_sgmii_riser_fdt_fixup(blob);
281 void board_lmb_reserve(struct lmb *lmb)
283 cpu_mp_lmb_reserve(lmb);