board/freescale/p1010rdb/p1010rdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <asm/processor.h>
  10 #include <asm/mmu.h>
  11 #include <asm/cache.h>
  12 #include <asm/immap_85xx.h>
  13 #include <asm/io.h>
  14 #include <env.h>
  15 #include <miiphy.h>
  16 #include <linux/libfdt.h>
  17 #include <fdt_support.h>
  18 #include <fsl_mdio.h>
  19 #include <tsec.h>
  20 #include <mmc.h>
  21 #include <netdev.h>
  22 #include <pci.h>
  23 #include <asm/fsl_serdes.h>
  24 #include <fsl_ifc.h>
  25 #include <asm/fsl_pci.h>
  26 #include <hwconfig.h>
  27 #include <i2c.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define GPIO4_PCIE_RESET_SET            0x08000000
  32 #define MUX_CPLD_CAN_UART               0x00
  33 #define MUX_CPLD_TDM                    0x01
  34 #define MUX_CPLD_SPICS0_FLASH           0x00
  35 #define MUX_CPLD_SPICS0_SLIC            0x02
  36 #define PMUXCR1_IFC_MASK       0x00ffff00
  37 #define PMUXCR1_SDHC_MASK      0x00fff000
  38 #define PMUXCR1_SDHC_ENABLE    0x00555000
  39
  40 enum {
  41         MUX_TYPE_IFC,
  42         MUX_TYPE_SDHC,
  43         MUX_TYPE_SPIFLASH,
  44         MUX_TYPE_TDM,
  45         MUX_TYPE_CAN,
  46         MUX_TYPE_CS0_NOR,
  47         MUX_TYPE_CS0_NAND,
  48 };
  49
  50 enum {
  51         I2C_READ_BANK,
  52         I2C_READ_PCB_VER,
  53 };
  54
  55 static uint sd_ifc_mux;
  56
  57 struct cpld_data {
  58         u8 cpld_ver; /* cpld revision */
  59 #if defined(CONFIG_TARGET_P1010RDB_PA)
  60         u8 pcba_ver; /* pcb revision number */
  61         u8 twindie_ddr3;
  62         u8 res1[6];
  63         u8 bank_sel; /* NOR Flash bank */
  64         u8 res2[5];
  65         u8 usb2_sel;
  66         u8 res3[1];
  67         u8 porsw_sel;
  68         u8 tdm_can_sel;
  69         u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
  70         u8 por0; /* POR Options */
  71         u8 por1; /* POR Options */
  72         u8 por2; /* POR Options */
  73         u8 por3; /* POR Options */
  74 #elif defined(CONFIG_TARGET_P1010RDB_PB)
  75         u8 rom_loc;
  76 #endif
  77 };
  78
  79 int board_early_init_f(void)
  80 {
  81         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  82         struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  83         /* Clock configuration to access CPLD using IFC(GPCM) */
  84         setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  85         /*
  86         * Reset PCIe slots via GPIO4
  87         */
  88         setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
  89         setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
  90
  91         return 0;
  92 }
  93
  94 int board_early_init_r(void)
  95 {
  96         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  97         int flash_esel = find_tlb_idx((void *)flashbase, 1);
  98
  99         /*
 100          * Remap Boot flash region to caching-inhibited
 101          * so that flash can be erased properly.
 102          */
 103
 104         /* Flush d-cache and invalidate i-cache of any FLASH data */
 105         flush_dcache();
 106         invalidate_icache();
 107
 108         if (flash_esel == -1) {
 109                 /* very unlikely unless something is messed up */
 110                 puts("Error: Could not find TLB for FLASH BASE\n");
 111                 flash_esel = 2; /* give our best effort to continue */
 112         } else {
 113                 /* invalidate existing TLB entry for flash */
 114                 disable_tlb(flash_esel);
 115         }
 116
 117         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 118                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 119                         0, flash_esel, BOOKE_PAGESZ_16M, 1);
 120
 121         set_tlb(1, flashbase + 0x1000000,
 122                         CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 123                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 124                         0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
 125         return 0;
 126 }
 127
 128 #ifdef CONFIG_PCI
 129 void pci_init_board(void)
 130 {
 131         fsl_pcie_init_board(0);
 132 }
 133 #endif /* ifdef CONFIG_PCI */
 134
 135 int config_board_mux(int ctrl_type)
 136 {
 137         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 138         u8 tmp;
 139
 140 #ifdef CONFIG_DM_I2C
 141         struct udevice *dev;
 142         int ret;
 143 #if defined(CONFIG_TARGET_P1010RDB_PA)
 144         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 145
 146         ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
 147                                       I2C_PCA9557_ADDR1, 1, &dev);
 148         if (ret) {
 149                 printf("%s: Cannot find udev for a bus %d\n",
 150                        __func__, I2C_PCA9557_BUS_NUM);
 151                 return ret;
 152         }
 153         switch (ctrl_type) {
 154         case MUX_TYPE_IFC:
 155                 tmp = 0xf0;
 156                 dm_i2c_write(dev, 3, &tmp, 1);
 157                 tmp = 0x01;
 158                 dm_i2c_write(dev, 1, &tmp, 1);
 159                 sd_ifc_mux = MUX_TYPE_IFC;
 160                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 161                 break;
 162         case MUX_TYPE_SDHC:
 163                 tmp = 0xf0;
 164                 dm_i2c_write(dev, 3, &tmp, 1);
 165                 tmp = 0x05;
 166                 dm_i2c_write(dev, 1, &tmp, 1);
 167                 sd_ifc_mux = MUX_TYPE_SDHC;
 168                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 169                                 PMUXCR1_SDHC_ENABLE);
 170                 break;
 171         case MUX_TYPE_SPIFLASH:
 172                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
 173                 break;
 174         case MUX_TYPE_TDM:
 175                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
 176                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
 177                 break;
 178         case MUX_TYPE_CAN:
 179                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
 180                 break;
 181         default:
 182                 break;
 183         }
 184 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 185         ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
 186                                       I2C_PCA9557_ADDR2, 1, &dev);
 187         if (ret) {
 188                 printf("%s: Cannot find udev for a bus %d\n",
 189                        __func__, I2C_PCA9557_BUS_NUM);
 190                 return ret;
 191         }
 192         switch (ctrl_type) {
 193         case MUX_TYPE_IFC:
 194                 dm_i2c_read(dev, 0, &tmp, 1);
 195                 clrbits_8(&tmp, 0x04);
 196                 dm_i2c_write(dev, 1, &tmp, 1);
 197                 dm_i2c_read(dev, 3, &tmp, 1);
 198                 clrbits_8(&tmp, 0x04);
 199                 dm_i2c_write(dev, 3, &tmp, 1);
 200                 sd_ifc_mux = MUX_TYPE_IFC;
 201                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 202                 break;
 203         case MUX_TYPE_SDHC:
 204                 dm_i2c_read(dev, 0, &tmp, 1);
 205                 setbits_8(&tmp, 0x04);
 206                 dm_i2c_write(dev, 1, &tmp, 1);
 207                 dm_i2c_read(dev, 3, &tmp, 1);
 208                 clrbits_8(&tmp, 0x04);
 209                 dm_i2c_write(dev, 3, &tmp, 1);
 210                 sd_ifc_mux = MUX_TYPE_SDHC;
 211                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 212                                 PMUXCR1_SDHC_ENABLE);
 213                 break;
 214         case MUX_TYPE_SPIFLASH:
 215                 dm_i2c_read(dev, 0, &tmp, 1);
 216                 clrbits_8(&tmp, 0x80);
 217                 dm_i2c_write(dev, 1, &tmp, 1);
 218                 dm_i2c_read(dev, 3, &tmp, 1);
 219                 clrbits_8(&tmp, 0x80);
 220                 dm_i2c_write(dev, 3, &tmp, 1);
 221                 break;
 222         case MUX_TYPE_TDM:
 223                 dm_i2c_read(dev, 0, &tmp, 1);
 224                 setbits_8(&tmp, 0x82);
 225                 dm_i2c_write(dev, 1, &tmp, 1);
 226                 dm_i2c_read(dev, 3, &tmp, 1);
 227                 clrbits_8(&tmp, 0x82);
 228                 dm_i2c_write(dev, 3, &tmp, 1);
 229                 break;
 230         case MUX_TYPE_CAN:
 231                 dm_i2c_read(dev, 0, &tmp, 1);
 232                 clrbits_8(&tmp, 0x02);
 233                 dm_i2c_write(dev, 1, &tmp, 1);
 234                 dm_i2c_read(dev, 3, &tmp, 1);
 235                 clrbits_8(&tmp, 0x02);
 236                 dm_i2c_write(dev, 3, &tmp, 1);
 237                 break;
 238         case MUX_TYPE_CS0_NOR:
 239                 dm_i2c_read(dev, 0, &tmp, 1);
 240                 clrbits_8(&tmp, 0x08);
 241                 dm_i2c_write(dev, 1, &tmp, 1);
 242                 dm_i2c_read(dev, 3, &tmp, 1);
 243                 clrbits_8(&tmp, 0x08);
 244                 dm_i2c_write(dev, 3, &tmp, 1);
 245                 break;
 246         case MUX_TYPE_CS0_NAND:
 247                 dm_i2c_read(dev, 0, &tmp, 1);
 248                 setbits_8(&tmp, 0x08);
 249                 dm_i2c_write(dev, 1, &tmp, 1);
 250                 dm_i2c_read(dev, 3, &tmp, 1);
 251                 clrbits_8(&tmp, 0x08);
 252                 dm_i2c_write(dev, 3, &tmp, 1);
 253                 break;
 254         default:
 255                 break;
 256         }
 257 #endif
 258 #else
 259 #if defined(CONFIG_TARGET_P1010RDB_PA)
 260         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 261
 262         switch (ctrl_type) {
 263         case MUX_TYPE_IFC:
 264                 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 265                 tmp = 0xf0;
 266                 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
 267                 tmp = 0x01;
 268                 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
 269                 sd_ifc_mux = MUX_TYPE_IFC;
 270                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 271                 break;
 272         case MUX_TYPE_SDHC:
 273                 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 274                 tmp = 0xf0;
 275                 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
 276                 tmp = 0x05;
 277                 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
 278                 sd_ifc_mux = MUX_TYPE_SDHC;
 279                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 280                                 PMUXCR1_SDHC_ENABLE);
 281                 break;
 282         case MUX_TYPE_SPIFLASH:
 283                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
 284                 break;
 285         case MUX_TYPE_TDM:
 286                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
 287                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
 288                 break;
 289         case MUX_TYPE_CAN:
 290                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
 291                 break;
 292         default:
 293                 break;
 294         }
 295 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 296         uint orig_bus = i2c_get_bus_num();
 297         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 298
 299         switch (ctrl_type) {
 300         case MUX_TYPE_IFC:
 301                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 302                 clrbits_8(&tmp, 0x04);
 303                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 304                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 305                 clrbits_8(&tmp, 0x04);
 306                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 307                 sd_ifc_mux = MUX_TYPE_IFC;
 308                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 309                 break;
 310         case MUX_TYPE_SDHC:
 311                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 312                 setbits_8(&tmp, 0x04);
 313                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 314                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 315                 clrbits_8(&tmp, 0x04);
 316                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 317                 sd_ifc_mux = MUX_TYPE_SDHC;
 318                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 319                                 PMUXCR1_SDHC_ENABLE);
 320                 break;
 321         case MUX_TYPE_SPIFLASH:
 322                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 323                 clrbits_8(&tmp, 0x80);
 324                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 325                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 326                 clrbits_8(&tmp, 0x80);
 327                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 328                 break;
 329         case MUX_TYPE_TDM:
 330                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 331                 setbits_8(&tmp, 0x82);
 332                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 333                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 334                 clrbits_8(&tmp, 0x82);
 335                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 336                 break;
 337         case MUX_TYPE_CAN:
 338                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 339                 clrbits_8(&tmp, 0x02);
 340                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 341                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 342                 clrbits_8(&tmp, 0x02);
 343                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 344                 break;
 345         case MUX_TYPE_CS0_NOR:
 346                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 347                 clrbits_8(&tmp, 0x08);
 348                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 349                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 350                 clrbits_8(&tmp, 0x08);
 351                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 352                 break;
 353         case MUX_TYPE_CS0_NAND:
 354                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 355                 setbits_8(&tmp, 0x08);
 356                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 357                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 358                 clrbits_8(&tmp, 0x08);
 359                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 360                 break;
 361         default:
 362                 break;
 363         }
 364         i2c_set_bus_num(orig_bus);
 365 #endif
 366 #endif
 367         return 0;
 368 }
 369
 370 #ifdef CONFIG_TARGET_P1010RDB_PB
 371 int i2c_pca9557_read(int type)
 372 {
 373         u8 val;
 374         int bus_num = I2C_PCA9557_BUS_NUM;
 375
 376 #ifdef CONFIG_DM_I2C
 377         struct udevice *dev;
 378         int ret;
 379
 380         ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
 381         if (ret) {
 382                 printf("%s: Cannot find udev for a bus %d\n",
 383                        __func__, bus_num);
 384                 return ret;
 385         }
 386         dm_i2c_read(dev, 0, &val, 1);
 387 #else
 388         i2c_set_bus_num(bus_num);
 389         i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
 390 #endif
 391
 392         switch (type) {
 393         case I2C_READ_BANK:
 394                 val = (val & 0x10) >> 4;
 395                 break;
 396         case I2C_READ_PCB_VER:
 397                 val = ((val & 0x60) >> 5) + 1;
 398                 break;
 399         default:
 400                 break;
 401         }
 402
 403         return val;
 404 }
 405 #endif
 406
 407 int checkboard(void)
 408 {
 409         struct cpu_type *cpu;
 410         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 411         u8 val;
 412
 413         cpu = gd->arch.cpu;
 414 #if defined(CONFIG_TARGET_P1010RDB_PA)
 415         printf("Board: %sRDB-PA, ", cpu->name);
 416 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 417         printf("Board: %sRDB-PB, ", cpu->name);
 418 #ifdef CONFIG_DM_I2C
 419         struct udevice *dev;
 420         int ret;
 421
 422         ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
 423                                       1, &dev);
 424         if (ret) {
 425                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 426                        I2C_PCA9557_BUS_NUM);
 427                 return ret;
 428         }
 429         val = 0x0;  /* no polarity inversion */
 430         dm_i2c_write(dev, 2, &val, 1);
 431 #else
 432         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 433         i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
 434         val = 0x0;  /* no polarity inversion */
 435         i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
 436 #endif
 437 #endif
 438
 439 #ifdef CONFIG_SDCARD
 440         /* switch to IFC to read info from CPLD */
 441         config_board_mux(MUX_TYPE_IFC);
 442 #endif
 443
 444 #if defined(CONFIG_TARGET_P1010RDB_PA)
 445         val = (in_8(&cpld_data->pcba_ver) & 0xf);
 446         printf("PCB: v%x.0\n", val);
 447 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 448         val = in_8(&cpld_data->cpld_ver);
 449         printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
 450         printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
 451         val = in_8(&cpld_data->rom_loc) & 0xf;
 452         puts("Boot from: ");
 453         switch (val) {
 454         case 0xf:
 455                 config_board_mux(MUX_TYPE_CS0_NOR);
 456                 printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
 457                 break;
 458         case 0xe:
 459                 puts("SDHC\n");
 460                 val = 0x60; /* set pca9557 pin input/output */
 461 #ifdef CONFIG_DM_I2C
 462                 dm_i2c_write(dev, 3, &val, 1);
 463 #else
 464                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
 465 #endif
 466                 break;
 467         case 0x5:
 468                 config_board_mux(MUX_TYPE_IFC);
 469                 config_board_mux(MUX_TYPE_CS0_NAND);
 470                 puts("NAND\n");
 471                 break;
 472         case 0x6:
 473                 config_board_mux(MUX_TYPE_IFC);
 474                 puts("SPI\n");
 475                 break;
 476         default:
 477                 puts("unknown\n");
 478                 break;
 479         }
 480 #endif
 481         return 0;
 482 }
 483
 484 int board_eth_init(bd_t *bis)
 485 {
 486 #ifdef CONFIG_TSEC_ENET
 487         struct fsl_pq_mdio_info mdio_info;
 488         struct tsec_info_struct tsec_info[4];
 489         struct cpu_type *cpu;
 490         int num = 0;
 491
 492         cpu = gd->arch.cpu;
 493
 494 #ifdef CONFIG_TSEC1
 495         SET_STD_TSEC_INFO(tsec_info[num], 1);
 496         num++;
 497 #endif
 498 #ifdef CONFIG_TSEC2
 499         SET_STD_TSEC_INFO(tsec_info[num], 2);
 500         num++;
 501 #endif
 502 #ifdef CONFIG_TSEC3
 503         /* P1014 and it's derivatives do not support eTSEC3 */
 504         if (cpu->soc_ver != SVR_P1014) {
 505                 SET_STD_TSEC_INFO(tsec_info[num], 3);
 506                 num++;
 507         }
 508 #endif
 509         if (!num) {
 510                 printf("No TSECs initialized\n");
 511                 return 0;
 512         }
 513
 514         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 515         mdio_info.name = DEFAULT_MII_NAME;
 516
 517         fsl_pq_mdio_init(bis, &mdio_info);
 518
 519         tsec_eth_init(bis, tsec_info, num);
 520 #endif
 521
 522         return pci_eth_init(bis);
 523 }
 524
 525 #if defined(CONFIG_OF_BOARD_SETUP)
 526 void fdt_del_flexcan(void *blob)
 527 {
 528         int nodeoff = 0;
 529
 530         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 531                                 "fsl,p1010-flexcan")) >= 0) {
 532                 fdt_del_node(blob, nodeoff);
 533         }
 534 }
 535
 536 void fdt_del_spi_flash(void *blob)
 537 {
 538         int nodeoff = 0;
 539
 540         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 541                                 "spansion,s25sl12801")) >= 0) {
 542                 fdt_del_node(blob, nodeoff);
 543         }
 544 }
 545
 546 void fdt_del_spi_slic(void *blob)
 547 {
 548         int nodeoff = 0;
 549
 550         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 551                                 "zarlink,le88266")) >= 0) {
 552                 fdt_del_node(blob, nodeoff);
 553         }
 554 }
 555
 556 void fdt_del_tdm(void *blob)
 557 {
 558         int nodeoff = 0;
 559
 560         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 561                                 "fsl,starlite-tdm")) >= 0) {
 562                 fdt_del_node(blob, nodeoff);
 563         }
 564 }
 565
 566 void fdt_del_sdhc(void *blob)
 567 {
 568         int nodeoff = 0;
 569
 570         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 571                         "fsl,esdhc")) >= 0) {
 572                 fdt_del_node(blob, nodeoff);
 573         }
 574 }
 575
 576 void fdt_del_ifc(void *blob)
 577 {
 578         int nodeoff = 0;
 579
 580         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 581                                 "fsl,ifc")) >= 0) {
 582                 fdt_del_node(blob, nodeoff);
 583         }
 584 }
 585
 586 void fdt_disable_uart1(void *blob)
 587 {
 588         int nodeoff;
 589
 590         nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
 591                                         CONFIG_SYS_NS16550_COM2);
 592
 593         if (nodeoff > 0) {
 594                 fdt_status_disabled(blob, nodeoff);
 595         } else {
 596                 printf("WARNING unable to set status for fsl,ns16550 "
 597                         "uart1: %s\n", fdt_strerror(nodeoff));
 598         }
 599 }
 600
 601 int ft_board_setup(void *blob, bd_t *bd)
 602 {
 603         phys_addr_t base;
 604         phys_size_t size;
 605         struct cpu_type *cpu;
 606
 607         cpu = gd->arch.cpu;
 608
 609         ft_cpu_setup(blob, bd);
 610
 611         base = env_get_bootm_low();
 612         size = env_get_bootm_size();
 613
 614 #if defined(CONFIG_PCI)
 615         FT_FSL_PCI_SETUP;
 616 #endif
 617
 618         fdt_fixup_memory(blob, (u64)base, (u64)size);
 619
 620 #if defined(CONFIG_HAS_FSL_DR_USB)
 621         fsl_fdt_fixup_dr_usb(blob, bd);
 622 #endif
 623
 624        /* P1014 and it's derivatives don't support CAN and eTSEC3 */
 625         if (cpu->soc_ver == SVR_P1014) {
 626                 fdt_del_flexcan(blob);
 627                 fdt_del_node_and_alias(blob, "ethernet2");
 628         }
 629
 630         /* Delete IFC node as IFC pins are multiplexing with SDHC */
 631         if (sd_ifc_mux != MUX_TYPE_IFC)
 632                 fdt_del_ifc(blob);
 633         else
 634                 fdt_del_sdhc(blob);
 635
 636         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 637                 fdt_del_tdm(blob);
 638                 fdt_del_spi_slic(blob);
 639         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 640                 fdt_del_flexcan(blob);
 641                 fdt_del_spi_flash(blob);
 642                 fdt_disable_uart1(blob);
 643         } else {
 644                 /*
 645                  * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
 646                  * explicitly, defaultly spi_cs_sel to spi-flash instead of
 647                  * to tdm/slic.
 648                  */
 649                 fdt_del_tdm(blob);
 650                 fdt_del_flexcan(blob);
 651                 fdt_disable_uart1(blob);
 652         }
 653
 654         return 0;
 655 }
 656 #endif
 657
 658 #ifdef CONFIG_SDCARD
 659 int board_mmc_init(bd_t *bis)
 660 {
 661         config_board_mux(MUX_TYPE_SDHC);
 662                 return -1;
 663 }
 664 #else
 665 void board_reset(void)
 666 {
 667         /* mux to IFC to enable CPLD for reset */
 668         if (sd_ifc_mux != MUX_TYPE_IFC)
 669                 config_board_mux(MUX_TYPE_IFC);
 670 }
 671 #endif
 672
 673
 674 int misc_init_r(void)
 675 {
 676         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 677
 678         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 679                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
 680                                 MPC85xx_PMUXCR_CAN1_UART |
 681                                 MPC85xx_PMUXCR_CAN2_TDM |
 682                                 MPC85xx_PMUXCR_CAN2_UART);
 683                 config_board_mux(MUX_TYPE_CAN);
 684         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 685                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
 686                                 MPC85xx_PMUXCR_CAN1_UART);
 687                 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
 688                                 MPC85xx_PMUXCR_CAN1_TDM);
 689                 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
 690                 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
 691                 config_board_mux(MUX_TYPE_TDM);
 692         } else {
 693                 /* defaultly spi_cs_sel to flash */
 694                 config_board_mux(MUX_TYPE_SPIFLASH);
 695         }
 696
 697         if (hwconfig("esdhc"))
 698                 config_board_mux(MUX_TYPE_SDHC);
 699         else if (hwconfig("ifc"))
 700                 config_board_mux(MUX_TYPE_IFC);
 701
 702 #ifdef CONFIG_TARGET_P1010RDB_PB
 703         setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
 704 #endif
 705         return 0;
 706 }
 707
 708 #ifndef CONFIG_SPL_BUILD
 709 static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 710                                 char * const argv[])
 711 {
 712         if (argc < 2)
 713                 return CMD_RET_USAGE;
 714         if (strcmp(argv[1], "ifc") == 0)
 715                 config_board_mux(MUX_TYPE_IFC);
 716         else if (strcmp(argv[1], "sdhc") == 0)
 717                 config_board_mux(MUX_TYPE_SDHC);
 718         else
 719                 return CMD_RET_USAGE;
 720         return 0;
 721 }
 722
 723 U_BOOT_CMD(
 724         mux, 2, 0, pin_mux_cmd,
 725         "configure multiplexing pin for IFC/SDHC bus in runtime",
 726         "bus_type (e.g. mux sdhc)"
 727 );
 728 #endif