board/freescale/p1010rdb/p1010rdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <image.h>
  10 #include <init.h>
  11 #include <net.h>
  12 #include <asm/processor.h>
  13 #include <asm/mmu.h>
  14 #include <asm/cache.h>
  15 #include <asm/immap_85xx.h>
  16 #include <asm/io.h>
  17 #include <env.h>
  18 #include <miiphy.h>
  19 #include <linux/libfdt.h>
  20 #include <fdt_support.h>
  21 #include <fsl_mdio.h>
  22 #include <tsec.h>
  23 #include <mmc.h>
  24 #include <netdev.h>
  25 #include <pci.h>
  26 #include <asm/fsl_serdes.h>
  27 #include <fsl_ifc.h>
  28 #include <asm/fsl_pci.h>
  29 #include <hwconfig.h>
  30 #include <i2c.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define GPIO4_PCIE_RESET_SET            0x08000000
  35 #define MUX_CPLD_CAN_UART               0x00
  36 #define MUX_CPLD_TDM                    0x01
  37 #define MUX_CPLD_SPICS0_FLASH           0x00
  38 #define MUX_CPLD_SPICS0_SLIC            0x02
  39 #define PMUXCR1_IFC_MASK       0x00ffff00
  40 #define PMUXCR1_SDHC_MASK      0x00fff000
  41 #define PMUXCR1_SDHC_ENABLE    0x00555000
  42
  43 enum {
  44         MUX_TYPE_IFC,
  45         MUX_TYPE_SDHC,
  46         MUX_TYPE_SPIFLASH,
  47         MUX_TYPE_TDM,
  48         MUX_TYPE_CAN,
  49         MUX_TYPE_CS0_NOR,
  50         MUX_TYPE_CS0_NAND,
  51 };
  52
  53 enum {
  54         I2C_READ_BANK,
  55         I2C_READ_PCB_VER,
  56 };
  57
  58 static uint sd_ifc_mux;
  59
  60 struct cpld_data {
  61         u8 cpld_ver; /* cpld revision */
  62 #if defined(CONFIG_TARGET_P1010RDB_PA)
  63         u8 pcba_ver; /* pcb revision number */
  64         u8 twindie_ddr3;
  65         u8 res1[6];
  66         u8 bank_sel; /* NOR Flash bank */
  67         u8 res2[5];
  68         u8 usb2_sel;
  69         u8 res3[1];
  70         u8 porsw_sel;
  71         u8 tdm_can_sel;
  72         u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
  73         u8 por0; /* POR Options */
  74         u8 por1; /* POR Options */
  75         u8 por2; /* POR Options */
  76         u8 por3; /* POR Options */
  77 #elif defined(CONFIG_TARGET_P1010RDB_PB)
  78         u8 rom_loc;
  79 #endif
  80 };
  81
  82 int board_early_init_f(void)
  83 {
  84         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  85         struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  86         /* Clock configuration to access CPLD using IFC(GPCM) */
  87         setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  88         /*
  89         * Reset PCIe slots via GPIO4
  90         */
  91         setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
  92         setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
  93
  94         return 0;
  95 }
  96
  97 int board_early_init_r(void)
  98 {
  99         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 100         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 101
 102         /*
 103          * Remap Boot flash region to caching-inhibited
 104          * so that flash can be erased properly.
 105          */
 106
 107         /* Flush d-cache and invalidate i-cache of any FLASH data */
 108         flush_dcache();
 109         invalidate_icache();
 110
 111         if (flash_esel == -1) {
 112                 /* very unlikely unless something is messed up */
 113                 puts("Error: Could not find TLB for FLASH BASE\n");
 114                 flash_esel = 2; /* give our best effort to continue */
 115         } else {
 116                 /* invalidate existing TLB entry for flash */
 117                 disable_tlb(flash_esel);
 118         }
 119
 120         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 121                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 122                         0, flash_esel, BOOKE_PAGESZ_16M, 1);
 123
 124         set_tlb(1, flashbase + 0x1000000,
 125                         CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 126                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 127                         0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
 128         return 0;
 129 }
 130
 131 #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
 132 void pci_init_board(void)
 133 {
 134         fsl_pcie_init_board(0);
 135 }
 136 #endif /* ifdef CONFIG_PCI */
 137
 138 int config_board_mux(int ctrl_type)
 139 {
 140         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 141         u8 tmp;
 142
 143 #ifdef CONFIG_DM_I2C
 144         struct udevice *dev;
 145         int ret;
 146 #if defined(CONFIG_TARGET_P1010RDB_PA)
 147         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 148
 149         ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
 150                                       I2C_PCA9557_ADDR1, 1, &dev);
 151         if (ret) {
 152                 printf("%s: Cannot find udev for a bus %d\n",
 153                        __func__, I2C_PCA9557_BUS_NUM);
 154                 return ret;
 155         }
 156         switch (ctrl_type) {
 157         case MUX_TYPE_IFC:
 158                 tmp = 0xf0;
 159                 dm_i2c_write(dev, 3, &tmp, 1);
 160                 tmp = 0x01;
 161                 dm_i2c_write(dev, 1, &tmp, 1);
 162                 sd_ifc_mux = MUX_TYPE_IFC;
 163                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 164                 break;
 165         case MUX_TYPE_SDHC:
 166                 tmp = 0xf0;
 167                 dm_i2c_write(dev, 3, &tmp, 1);
 168                 tmp = 0x05;
 169                 dm_i2c_write(dev, 1, &tmp, 1);
 170                 sd_ifc_mux = MUX_TYPE_SDHC;
 171                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 172                                 PMUXCR1_SDHC_ENABLE);
 173                 break;
 174         case MUX_TYPE_SPIFLASH:
 175                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
 176                 break;
 177         case MUX_TYPE_TDM:
 178                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
 179                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
 180                 break;
 181         case MUX_TYPE_CAN:
 182                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
 183                 break;
 184         default:
 185                 break;
 186         }
 187 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 188         ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
 189                                       I2C_PCA9557_ADDR2, 1, &dev);
 190         if (ret) {
 191                 printf("%s: Cannot find udev for a bus %d\n",
 192                        __func__, I2C_PCA9557_BUS_NUM);
 193                 return ret;
 194         }
 195         switch (ctrl_type) {
 196         case MUX_TYPE_IFC:
 197                 dm_i2c_read(dev, 0, &tmp, 1);
 198                 clrbits_8(&tmp, 0x04);
 199                 dm_i2c_write(dev, 1, &tmp, 1);
 200                 dm_i2c_read(dev, 3, &tmp, 1);
 201                 clrbits_8(&tmp, 0x04);
 202                 dm_i2c_write(dev, 3, &tmp, 1);
 203                 sd_ifc_mux = MUX_TYPE_IFC;
 204                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 205                 break;
 206         case MUX_TYPE_SDHC:
 207                 dm_i2c_read(dev, 0, &tmp, 1);
 208                 setbits_8(&tmp, 0x04);
 209                 dm_i2c_write(dev, 1, &tmp, 1);
 210                 dm_i2c_read(dev, 3, &tmp, 1);
 211                 clrbits_8(&tmp, 0x04);
 212                 dm_i2c_write(dev, 3, &tmp, 1);
 213                 sd_ifc_mux = MUX_TYPE_SDHC;
 214                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 215                                 PMUXCR1_SDHC_ENABLE);
 216                 break;
 217         case MUX_TYPE_SPIFLASH:
 218                 dm_i2c_read(dev, 0, &tmp, 1);
 219                 clrbits_8(&tmp, 0x80);
 220                 dm_i2c_write(dev, 1, &tmp, 1);
 221                 dm_i2c_read(dev, 3, &tmp, 1);
 222                 clrbits_8(&tmp, 0x80);
 223                 dm_i2c_write(dev, 3, &tmp, 1);
 224                 break;
 225         case MUX_TYPE_TDM:
 226                 dm_i2c_read(dev, 0, &tmp, 1);
 227                 setbits_8(&tmp, 0x82);
 228                 dm_i2c_write(dev, 1, &tmp, 1);
 229                 dm_i2c_read(dev, 3, &tmp, 1);
 230                 clrbits_8(&tmp, 0x82);
 231                 dm_i2c_write(dev, 3, &tmp, 1);
 232                 break;
 233         case MUX_TYPE_CAN:
 234                 dm_i2c_read(dev, 0, &tmp, 1);
 235                 clrbits_8(&tmp, 0x02);
 236                 dm_i2c_write(dev, 1, &tmp, 1);
 237                 dm_i2c_read(dev, 3, &tmp, 1);
 238                 clrbits_8(&tmp, 0x02);
 239                 dm_i2c_write(dev, 3, &tmp, 1);
 240                 break;
 241         case MUX_TYPE_CS0_NOR:
 242                 dm_i2c_read(dev, 0, &tmp, 1);
 243                 clrbits_8(&tmp, 0x08);
 244                 dm_i2c_write(dev, 1, &tmp, 1);
 245                 dm_i2c_read(dev, 3, &tmp, 1);
 246                 clrbits_8(&tmp, 0x08);
 247                 dm_i2c_write(dev, 3, &tmp, 1);
 248                 break;
 249         case MUX_TYPE_CS0_NAND:
 250                 dm_i2c_read(dev, 0, &tmp, 1);
 251                 setbits_8(&tmp, 0x08);
 252                 dm_i2c_write(dev, 1, &tmp, 1);
 253                 dm_i2c_read(dev, 3, &tmp, 1);
 254                 clrbits_8(&tmp, 0x08);
 255                 dm_i2c_write(dev, 3, &tmp, 1);
 256                 break;
 257         default:
 258                 break;
 259         }
 260 #endif
 261 #else
 262 #if defined(CONFIG_TARGET_P1010RDB_PA)
 263         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 264
 265         switch (ctrl_type) {
 266         case MUX_TYPE_IFC:
 267                 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 268                 tmp = 0xf0;
 269                 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
 270                 tmp = 0x01;
 271                 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
 272                 sd_ifc_mux = MUX_TYPE_IFC;
 273                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 274                 break;
 275         case MUX_TYPE_SDHC:
 276                 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 277                 tmp = 0xf0;
 278                 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
 279                 tmp = 0x05;
 280                 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
 281                 sd_ifc_mux = MUX_TYPE_SDHC;
 282                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 283                                 PMUXCR1_SDHC_ENABLE);
 284                 break;
 285         case MUX_TYPE_SPIFLASH:
 286                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
 287                 break;
 288         case MUX_TYPE_TDM:
 289                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
 290                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
 291                 break;
 292         case MUX_TYPE_CAN:
 293                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
 294                 break;
 295         default:
 296                 break;
 297         }
 298 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 299         uint orig_bus = i2c_get_bus_num();
 300         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 301
 302         switch (ctrl_type) {
 303         case MUX_TYPE_IFC:
 304                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 305                 clrbits_8(&tmp, 0x04);
 306                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 307                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 308                 clrbits_8(&tmp, 0x04);
 309                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 310                 sd_ifc_mux = MUX_TYPE_IFC;
 311                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 312                 break;
 313         case MUX_TYPE_SDHC:
 314                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 315                 setbits_8(&tmp, 0x04);
 316                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 317                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 318                 clrbits_8(&tmp, 0x04);
 319                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 320                 sd_ifc_mux = MUX_TYPE_SDHC;
 321                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 322                                 PMUXCR1_SDHC_ENABLE);
 323                 break;
 324         case MUX_TYPE_SPIFLASH:
 325                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 326                 clrbits_8(&tmp, 0x80);
 327                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 328                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 329                 clrbits_8(&tmp, 0x80);
 330                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 331                 break;
 332         case MUX_TYPE_TDM:
 333                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 334                 setbits_8(&tmp, 0x82);
 335                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 336                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 337                 clrbits_8(&tmp, 0x82);
 338                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 339                 break;
 340         case MUX_TYPE_CAN:
 341                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 342                 clrbits_8(&tmp, 0x02);
 343                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 344                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 345                 clrbits_8(&tmp, 0x02);
 346                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 347                 break;
 348         case MUX_TYPE_CS0_NOR:
 349                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 350                 clrbits_8(&tmp, 0x08);
 351                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 352                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 353                 clrbits_8(&tmp, 0x08);
 354                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 355                 break;
 356         case MUX_TYPE_CS0_NAND:
 357                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 358                 setbits_8(&tmp, 0x08);
 359                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 360                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 361                 clrbits_8(&tmp, 0x08);
 362                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 363                 break;
 364         default:
 365                 break;
 366         }
 367         i2c_set_bus_num(orig_bus);
 368 #endif
 369 #endif
 370         return 0;
 371 }
 372
 373 #ifdef CONFIG_TARGET_P1010RDB_PB
 374 int i2c_pca9557_read(int type)
 375 {
 376         u8 val;
 377         int bus_num = I2C_PCA9557_BUS_NUM;
 378
 379 #ifdef CONFIG_DM_I2C
 380         struct udevice *dev;
 381         int ret;
 382
 383         ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
 384         if (ret) {
 385                 printf("%s: Cannot find udev for a bus %d\n",
 386                        __func__, bus_num);
 387                 return ret;
 388         }
 389         dm_i2c_read(dev, 0, &val, 1);
 390 #else
 391         i2c_set_bus_num(bus_num);
 392         i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
 393 #endif
 394
 395         switch (type) {
 396         case I2C_READ_BANK:
 397                 val = (val & 0x10) >> 4;
 398                 break;
 399         case I2C_READ_PCB_VER:
 400                 val = ((val & 0x60) >> 5) + 1;
 401                 break;
 402         default:
 403                 break;
 404         }
 405
 406         return val;
 407 }
 408 #endif
 409
 410 int checkboard(void)
 411 {
 412         struct cpu_type *cpu;
 413         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 414         u8 val;
 415
 416         cpu = gd->arch.cpu;
 417 #if defined(CONFIG_TARGET_P1010RDB_PA)
 418         printf("Board: %sRDB-PA, ", cpu->name);
 419 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 420         printf("Board: %sRDB-PB, ", cpu->name);
 421 #ifdef CONFIG_DM_I2C
 422         struct udevice *dev;
 423         int ret;
 424
 425         ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
 426                                       1, &dev);
 427         if (ret) {
 428                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 429                        I2C_PCA9557_BUS_NUM);
 430                 return ret;
 431         }
 432         val = 0x0;  /* no polarity inversion */
 433         dm_i2c_write(dev, 2, &val, 1);
 434 #else
 435         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 436         i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
 437         val = 0x0;  /* no polarity inversion */
 438         i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
 439 #endif
 440 #endif
 441
 442 #ifdef CONFIG_SDCARD
 443         /* switch to IFC to read info from CPLD */
 444         config_board_mux(MUX_TYPE_IFC);
 445 #endif
 446
 447 #if defined(CONFIG_TARGET_P1010RDB_PA)
 448         val = (in_8(&cpld_data->pcba_ver) & 0xf);
 449         printf("PCB: v%x.0\n", val);
 450 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 451         val = in_8(&cpld_data->cpld_ver);
 452         printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
 453         printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
 454         val = in_8(&cpld_data->rom_loc) & 0xf;
 455         puts("Boot from: ");
 456         switch (val) {
 457         case 0xf:
 458                 config_board_mux(MUX_TYPE_CS0_NOR);
 459                 printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
 460                 break;
 461         case 0xe:
 462                 puts("SDHC\n");
 463                 val = 0x60; /* set pca9557 pin input/output */
 464 #ifdef CONFIG_DM_I2C
 465                 dm_i2c_write(dev, 3, &val, 1);
 466 #else
 467                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
 468 #endif
 469                 break;
 470         case 0x5:
 471                 config_board_mux(MUX_TYPE_IFC);
 472                 config_board_mux(MUX_TYPE_CS0_NAND);
 473                 puts("NAND\n");
 474                 break;
 475         case 0x6:
 476                 config_board_mux(MUX_TYPE_IFC);
 477                 puts("SPI\n");
 478                 break;
 479         default:
 480                 puts("unknown\n");
 481                 break;
 482         }
 483 #endif
 484         return 0;
 485 }
 486
 487 #ifndef CONFIG_DM_ETH
 488 int board_eth_init(struct bd_info *bis)
 489 {
 490 #ifdef CONFIG_TSEC_ENET
 491         struct fsl_pq_mdio_info mdio_info;
 492         struct tsec_info_struct tsec_info[4];
 493         struct cpu_type *cpu;
 494         int num = 0;
 495
 496         cpu = gd->arch.cpu;
 497
 498 #ifdef CONFIG_TSEC1
 499         SET_STD_TSEC_INFO(tsec_info[num], 1);
 500         num++;
 501 #endif
 502 #ifdef CONFIG_TSEC2
 503         SET_STD_TSEC_INFO(tsec_info[num], 2);
 504         num++;
 505 #endif
 506 #ifdef CONFIG_TSEC3
 507         /* P1014 and it's derivatives do not support eTSEC3 */
 508         if (cpu->soc_ver != SVR_P1014) {
 509                 SET_STD_TSEC_INFO(tsec_info[num], 3);
 510                 num++;
 511         }
 512 #endif
 513         if (!num) {
 514                 printf("No TSECs initialized\n");
 515                 return 0;
 516         }
 517
 518         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 519         mdio_info.name = DEFAULT_MII_NAME;
 520
 521         fsl_pq_mdio_init(bis, &mdio_info);
 522
 523         tsec_eth_init(bis, tsec_info, num);
 524 #endif
 525
 526         return pci_eth_init(bis);
 527 }
 528 #endif
 529
 530 #if defined(CONFIG_OF_BOARD_SETUP)
 531 void fdt_del_flexcan(void *blob)
 532 {
 533         int nodeoff = 0;
 534
 535         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 536                                 "fsl,p1010-flexcan")) >= 0) {
 537                 fdt_del_node(blob, nodeoff);
 538         }
 539 }
 540
 541 void fdt_del_spi_flash(void *blob)
 542 {
 543         int nodeoff = 0;
 544
 545         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 546                                 "spansion,s25sl12801")) >= 0) {
 547                 fdt_del_node(blob, nodeoff);
 548         }
 549 }
 550
 551 void fdt_del_spi_slic(void *blob)
 552 {
 553         int nodeoff = 0;
 554
 555         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 556                                 "zarlink,le88266")) >= 0) {
 557                 fdt_del_node(blob, nodeoff);
 558         }
 559 }
 560
 561 void fdt_del_tdm(void *blob)
 562 {
 563         int nodeoff = 0;
 564
 565         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 566                                 "fsl,starlite-tdm")) >= 0) {
 567                 fdt_del_node(blob, nodeoff);
 568         }
 569 }
 570
 571 void fdt_del_sdhc(void *blob)
 572 {
 573         int nodeoff = 0;
 574
 575         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 576                         "fsl,esdhc")) >= 0) {
 577                 fdt_del_node(blob, nodeoff);
 578         }
 579 }
 580
 581 void fdt_del_ifc(void *blob)
 582 {
 583         int nodeoff = 0;
 584
 585         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 586                                 "fsl,ifc")) >= 0) {
 587                 fdt_del_node(blob, nodeoff);
 588         }
 589 }
 590
 591 void fdt_disable_uart1(void *blob)
 592 {
 593         int nodeoff;
 594
 595         nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
 596                                         CONFIG_SYS_NS16550_COM2);
 597
 598         if (nodeoff > 0) {
 599                 fdt_status_disabled(blob, nodeoff);
 600         } else {
 601                 printf("WARNING unable to set status for fsl,ns16550 "
 602                         "uart1: %s\n", fdt_strerror(nodeoff));
 603         }
 604 }
 605
 606 int ft_board_setup(void *blob, struct bd_info *bd)
 607 {
 608         phys_addr_t base;
 609         phys_size_t size;
 610         struct cpu_type *cpu;
 611
 612         cpu = gd->arch.cpu;
 613
 614         ft_cpu_setup(blob, bd);
 615
 616         base = env_get_bootm_low();
 617         size = env_get_bootm_size();
 618
 619 #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
 620         FT_FSL_PCI_SETUP;
 621 #endif
 622
 623         fdt_fixup_memory(blob, (u64)base, (u64)size);
 624
 625 #if defined(CONFIG_HAS_FSL_DR_USB)
 626         fsl_fdt_fixup_dr_usb(blob, bd);
 627 #endif
 628
 629        /* P1014 and it's derivatives don't support CAN and eTSEC3 */
 630         if (cpu->soc_ver == SVR_P1014) {
 631                 fdt_del_flexcan(blob);
 632                 fdt_del_node_and_alias(blob, "ethernet2");
 633         }
 634
 635         /* Delete IFC node as IFC pins are multiplexing with SDHC */
 636         if (sd_ifc_mux != MUX_TYPE_IFC)
 637                 fdt_del_ifc(blob);
 638         else
 639                 fdt_del_sdhc(blob);
 640
 641         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 642                 fdt_del_tdm(blob);
 643                 fdt_del_spi_slic(blob);
 644         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 645                 fdt_del_flexcan(blob);
 646                 fdt_del_spi_flash(blob);
 647                 fdt_disable_uart1(blob);
 648         } else {
 649                 /*
 650                  * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
 651                  * explicitly, defaultly spi_cs_sel to spi-flash instead of
 652                  * to tdm/slic.
 653                  */
 654                 fdt_del_tdm(blob);
 655                 fdt_del_flexcan(blob);
 656                 fdt_disable_uart1(blob);
 657         }
 658
 659         return 0;
 660 }
 661 #endif
 662
 663 #ifdef CONFIG_SDCARD
 664 int board_mmc_init(struct bd_info *bis)
 665 {
 666         config_board_mux(MUX_TYPE_SDHC);
 667                 return -1;
 668 }
 669 #else
 670 void board_reset(void)
 671 {
 672         /* mux to IFC to enable CPLD for reset */
 673         if (sd_ifc_mux != MUX_TYPE_IFC)
 674                 config_board_mux(MUX_TYPE_IFC);
 675 }
 676 #endif
 677
 678
 679 int misc_init_r(void)
 680 {
 681         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 682
 683         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 684                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
 685                                 MPC85xx_PMUXCR_CAN1_UART |
 686                                 MPC85xx_PMUXCR_CAN2_TDM |
 687                                 MPC85xx_PMUXCR_CAN2_UART);
 688                 config_board_mux(MUX_TYPE_CAN);
 689         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 690                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
 691                                 MPC85xx_PMUXCR_CAN1_UART);
 692                 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
 693                                 MPC85xx_PMUXCR_CAN1_TDM);
 694                 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
 695                 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
 696                 config_board_mux(MUX_TYPE_TDM);
 697         } else {
 698                 /* defaultly spi_cs_sel to flash */
 699                 config_board_mux(MUX_TYPE_SPIFLASH);
 700         }
 701
 702         if (hwconfig("esdhc"))
 703                 config_board_mux(MUX_TYPE_SDHC);
 704         else if (hwconfig("ifc"))
 705                 config_board_mux(MUX_TYPE_IFC);
 706
 707 #ifdef CONFIG_TARGET_P1010RDB_PB
 708         setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
 709 #endif
 710         return 0;
 711 }
 712
 713 #ifndef CONFIG_SPL_BUILD
 714 static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
 715                        char *const argv[])
 716 {
 717         if (argc < 2)
 718                 return CMD_RET_USAGE;
 719         if (strcmp(argv[1], "ifc") == 0)
 720                 config_board_mux(MUX_TYPE_IFC);
 721         else if (strcmp(argv[1], "sdhc") == 0)
 722                 config_board_mux(MUX_TYPE_SDHC);
 723         else
 724                 return CMD_RET_USAGE;
 725         return 0;
 726 }
 727
 728 U_BOOT_CMD(
 729         mux, 2, 0, pin_mux_cmd,
 730         "configure multiplexing pin for IFC/SDHC bus in runtime",
 731         "bus_type (e.g. mux sdhc)"
 732 );
 733 #endif