board/freescale/p1010rdb/ddr.c

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/mmu.h>
  25 #include <asm/immap_85xx.h>
  26 #include <asm/processor.h>
  27 #include <asm/fsl_ddr_sdram.h>
  28 #include <asm/fsl_ddr_dimm_params.h>
  29 #include <asm/io.h>
  30 #include <asm/fsl_law.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #ifndef CONFIG_SYS_DDR_RAW_TIMING
  35 #define CONFIG_SYS_DRAM_SIZE    1024
  36
  37 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
  38         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  39         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  40         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  41         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
  42         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
  43         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
  44         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
  45         .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  46         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  47         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
  48         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
  49         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  50         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
  51         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  52         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
  53         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  54         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  55         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  56         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  57         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  58         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
  59         .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  60         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  61         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  62 };
  63
  64 fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
  65         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  66         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  67         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  68         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
  69         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
  70         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
  71         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
  72         .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  73         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  74         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
  75         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
  76         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  77         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
  78         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  79         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
  80         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  81         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  82         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  83         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  84         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  85         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667,
  86         .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  87         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  88         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  89 };
  90
  91 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
  92         {750, 850, &ddr_cfg_regs_800},
  93         {607, 749, &ddr_cfg_regs_667},
  94         {0, 0, NULL}
  95 };
  96
  97 unsigned long get_sdram_size(void)
  98 {
  99         struct cpu_type *cpu;
 100         phys_size_t ddr_size;
 101
 102         cpu = gd->cpu;
 103         /* P1014 and it's derivatives support max 16it DDR width */
 104         if (cpu->soc_ver == SVR_P1014)
 105                 ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
 106         else
 107                 ddr_size = CONFIG_SYS_DRAM_SIZE;
 108
 109         return ddr_size;
 110 }
 111
 112 /*
 113  * Fixed sdram init -- doesn't use serial presence detect.
 114  */
 115 phys_size_t fixed_sdram(void)
 116 {
 117         int i;
 118         char buf[32];
 119         fsl_ddr_cfg_regs_t ddr_cfg_regs;
 120         phys_size_t ddr_size;
 121         ulong ddr_freq, ddr_freq_mhz;
 122         struct cpu_type *cpu;
 123
 124 #if defined(CONFIG_SYS_RAMBOOT)
 125         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 126 #endif
 127
 128         ddr_freq = get_ddr_freq(0);
 129         ddr_freq_mhz = ddr_freq / 1000000;
 130
 131         printf("Configuring DDR for %s MT/s data rate\n",
 132                                 strmhz(buf, ddr_freq));
 133
 134         for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
 135                 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
 136                    (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
 137                         memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
 138                                                         sizeof(ddr_cfg_regs));
 139                         break;
 140                 }
 141         }
 142
 143         if (fixed_ddr_parm_0[i].max_freq == 0)
 144                 panic("Unsupported DDR data rate %s MT/s data rate\n",
 145                                         strmhz(buf, ddr_freq));
 146
 147         cpu = gd->cpu;
 148         /* P1014 and it's derivatives support max 16bit DDR width */
 149         if (cpu->soc_ver == SVR_P1014) {
 150                 ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
 151                 ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1;
 152                 ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000;
 153                 ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000;
 154         }
 155
 156         ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 157         fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
 158
 159         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
 160                                         LAW_TRGT_IF_DDR_1) < 0) {
 161                 printf("ERROR setting Local Access Windows for DDR\n");
 162                 return 0;
 163         }
 164
 165         return ddr_size;
 166 }
 167
 168 #else /* CONFIG_SYS_DDR_RAW_TIMING */
 169 /*
 170  * Samsung K4B2G0846C-HCF8
 171  * The following timing are for "downshift"
 172  * i.e. to use CL9 part as CL7
 173  * otherwise, tAA, tRCD, tRP will be 13500ps
 174  * and tRC will be 49500ps
 175  */
 176 dimm_params_t ddr_raw_timing = {
 177         .n_ranks = 1,
 178         .rank_density = 1073741824u,
 179         .capacity = 1073741824u,
 180         .primary_sdram_width = 32,
 181         .ec_sdram_width = 0,
 182         .registered_dimm = 0,
 183         .mirrored_dimm = 0,
 184         .n_row_addr = 15,
 185         .n_col_addr = 10,
 186         .n_banks_per_sdram_device = 8,
 187         .edc_config = 0,
 188         .burst_lengths_bitmask = 0x0c,
 189
 190         .tCKmin_X_ps = 1875,
 191         .caslat_X = 0x1e << 4,  /* 5,6,7,8 */
 192         .tAA_ps = 13125,
 193         .tWR_ps = 15000,
 194         .tRCD_ps = 13125,
 195         .tRRD_ps = 7500,
 196         .tRP_ps = 13125,
 197         .tRAS_ps = 37500,
 198         .tRC_ps = 50625,
 199         .tRFC_ps = 160000,
 200         .tWTR_ps = 7500,
 201         .tRTP_ps = 7500,
 202         .refresh_rate_ps = 7800000,
 203         .tFAW_ps = 37500,
 204 };
 205
 206 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 207                 unsigned int controller_number,
 208                 unsigned int dimm_number)
 209 {
 210         const char dimm_model[] = "Fixed DDR on board";
 211
 212         if ((controller_number == 0) && (dimm_number == 0)) {
 213                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
 214                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 215                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
 216         }
 217
 218         return 0;
 219 }
 220
 221 void fsl_ddr_board_options(memctl_options_t *popts,
 222                                 dimm_params_t *pdimm,
 223                                 unsigned int ctrl_num)
 224 {
 225         struct cpu_type *cpu;
 226         int i;
 227         popts->clk_adjust = 6;
 228         popts->cpo_override = 0x1f;
 229         popts->write_data_delay = 2;
 230         popts->half_strength_driver_enable = 1;
 231         /* Write leveling override */
 232         popts->wrlvl_en = 1;
 233         popts->wrlvl_override = 1;
 234         popts->wrlvl_sample = 0xf;
 235         popts->wrlvl_start = 0x8;
 236         popts->trwt_override = 1;
 237         popts->trwt = 0;
 238
 239         cpu = gd->cpu;
 240         /* P1014 and it's derivatives support max 16it DDR width */
 241         if (cpu->soc_ver == SVR_P1014)
 242                 popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
 243
 244         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 245                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 246                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 247         }
 248 }
 249
 250 #endif /* CONFIG_SYS_DDR_RAW_TIMING */