1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx7-pins.h>
11 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/iomux-v3.h>
15 #include <linux/sizes.h>
17 #include <fsl_esdhc_imx.h>
20 #include <power/pmic.h>
21 #include <power/pfuze3000_pmic.h>
22 #include "../common/pfuze.h"
24 #include <asm/mach-imx/mxc_i2c.h>
25 #include <asm/arch/crm_regs.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
30 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
32 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
33 PAD_CTL_DSE_3P3V_49OHM)
35 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
37 #define SPI_PAD_CTRL \
38 (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
40 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
43 static iomux_v3_cfg_t const ecspi3_pads[] = {
44 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
45 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
46 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
47 MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
50 int board_spi_cs_gpio(unsigned bus, unsigned cs)
52 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;
55 static void setup_spi(void)
57 imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
63 gd->ram_size = PHYS_SDRAM_SIZE;
68 static iomux_v3_cfg_t const wdog_pads[] = {
69 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
72 static iomux_v3_cfg_t const uart1_pads[] = {
73 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
74 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
77 #ifdef CONFIG_NAND_MXS
78 static iomux_v3_cfg_t const gpmi_pads[] = {
79 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
80 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
81 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
82 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
83 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
84 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
85 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
86 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
87 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
88 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
89 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
90 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
91 MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
92 MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
93 MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
94 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
95 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
96 MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
97 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
100 static void setup_gpmi_nand(void)
102 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
104 /* NAND_USDHC_BUS_CLK is set in rom */
109 #ifdef CONFIG_VIDEO_MXS
110 static iomux_v3_cfg_t const lcd_pads[] = {
111 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
112 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
113 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
114 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
115 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
116 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
117 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
118 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
119 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
120 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
121 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
122 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
123 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
124 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
125 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
126 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
127 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
128 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
129 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
130 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
131 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
132 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
133 MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
134 MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
135 MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
136 MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
137 MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
138 MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
140 MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
143 static iomux_v3_cfg_t const pwm_pads[] = {
144 /* Use GPIO for Brightness adjustment, duty cycle = period */
145 MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
148 static int setup_lcd(void)
150 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
152 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
155 gpio_request(IMX_GPIO_NR(3, 4), "lcd reset");
156 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
158 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
160 /* Set Brightness to high */
161 gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight");
162 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
168 static void setup_iomux_uart(void)
170 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
173 int board_mmc_get_env_dev(int devno)
181 int mmc_map_to_kernel_blk(int dev_no)
189 #ifdef CONFIG_FEC_MXC
190 static int setup_fec(void)
192 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
193 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
195 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
196 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
197 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
198 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
200 return set_clk_enet(ENET_125MHZ);
203 int board_phy_config(struct phy_device *phydev)
205 /* enable rgmii rxc skew and phy mode select to RGMII copper */
206 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
207 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
208 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
209 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
211 if (phydev->drv->config)
212 phydev->drv->config(phydev);
217 #ifdef CONFIG_FSL_QSPI
218 int board_qspi_init(void)
227 int board_early_init_f(void)
236 /* address of boot parameters */
237 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
239 #ifdef CONFIG_FEC_MXC
243 #ifdef CONFIG_NAND_MXS
247 #ifdef CONFIG_VIDEO_MXS
251 #ifdef CONFIG_FSL_QSPI
255 #ifdef CONFIG_MXC_SPI
262 #ifdef CONFIG_DM_PMIC
263 int power_init_board(void)
266 int ret, dev_id, rev_id;
268 ret = pmic_get("pfuze3000@8", &dev);
274 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
275 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
276 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
278 pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
281 * Set the voltage of VLDO4 output to 2.8V which feeds
282 * the MIPI DSI and MIPI CSI inputs.
284 pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
290 int board_late_init(void)
292 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
294 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
296 set_wdog_reset(wdog);
299 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
300 * since we use PMIC_PWRON to reset the board.
302 clrsetbits_le16(&wdog->wcr, 0, 0x10);
311 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
316 printf("Board: i.MX7D SABRESD in %s mode\n", mode);