board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <init.h>
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/iomux.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/mx6ul_pins.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/mxc_i2c.h>
  18 #include <asm/io.h>
  19 #include <common.h>
  20 #include <env.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <i2c.h>
  23 #include <miiphy.h>
  24 #include <linux/sizes.h>
  25 #include <mmc.h>
  26 #include <netdev.h>
  27 #include <power/pmic.h>
  28 #include <power/pfuze3000_pmic.h>
  29 #include "../common/pfuze.h"
  30 #include <usb.h>
  31 #include <usb/ehci-ci.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  36         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  37         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  40         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  41         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  42         PAD_CTL_ODE)
  43
  44 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  45         PAD_CTL_SPEED_HIGH   |                                  \
  46         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  47
  48 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  49         PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  50
  51 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  52         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  53
  54 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  55
  56 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  57         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  58         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  59
  60 #ifdef CONFIG_DM_PMIC
  61 int power_init_board(void)
  62 {
  63         struct udevice *dev;
  64         int ret, dev_id, rev_id;
  65         unsigned int reg;
  66
  67         ret = pmic_get("pfuze3000", &dev);
  68         if (ret == -ENODEV)
  69                 return 0;
  70         if (ret != 0)
  71                 return ret;
  72
  73         dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  74         rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  75         printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  76
  77         /* disable Low Power Mode during standby mode */
  78         reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
  79         reg |= 0x1;
  80         pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
  81
  82         /* SW1B step ramp up time from 2us to 4us/25mV */
  83         pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
  84
  85         /* SW1B mode to APS/PFM */
  86         pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
  87
  88         /* SW1B standby voltage set to 0.975V */
  89         pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
  90
  91         return 0;
  92 }
  93 #endif
  94
  95 int dram_init(void)
  96 {
  97         gd->ram_size = imx_ddr_size();
  98
  99         return 0;
 100 }
 101
 102 static iomux_v3_cfg_t const uart1_pads[] = {
 103         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 104         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 105 };
 106
 107
 108 static void setup_iomux_uart(void)
 109 {
 110         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 111 }
 112
 113 #ifdef CONFIG_FSL_QSPI
 114 static int board_qspi_init(void)
 115 {
 116         /* Set the clock */
 117         enable_qspi_clk(0);
 118
 119         return 0;
 120 }
 121 #endif
 122
 123 #ifdef CONFIG_SPL_BUILD
 124
 125 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 126         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 127         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 128
 129 static iomux_v3_cfg_t const usdhc2_pads[] = {
 130         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136 };
 137
 138 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 139         {USDHC2_BASE_ADDR, 0, 4},
 140 };
 141
 142 int board_mmc_getcd(struct mmc *mmc)
 143 {
 144         return 1;
 145 }
 146
 147 int board_mmc_init(bd_t *bis)
 148 {
 149         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 150         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 151         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 152 }
 153 #endif
 154
 155 #ifdef CONFIG_USB_EHCI_MX6
 156 #ifndef CONFIG_DM_USB
 157
 158 #define USB_OTHERREGS_OFFSET    0x800
 159 #define UCTRL_PWR_POL           (1 << 9)
 160
 161 static iomux_v3_cfg_t const usb_otg_pads[] = {
 162         MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
 163 };
 164
 165 /* At default the 3v3 enables the MIC2026 for VBUS power */
 166 static void setup_usb(void)
 167 {
 168         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 169                                          ARRAY_SIZE(usb_otg_pads));
 170 }
 171
 172 int board_usb_phy_mode(int port)
 173 {
 174         if (port == 1)
 175                 return USB_INIT_HOST;
 176         else
 177                 return usb_phy_mode(port);
 178 }
 179
 180 int board_ehci_hcd_init(int port)
 181 {
 182         u32 *usbnc_usb_ctrl;
 183
 184         if (port > 1)
 185                 return -EINVAL;
 186
 187         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 188                                  port * 4);
 189
 190         /* Set Power polarity */
 191         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 192
 193         return 0;
 194 }
 195 #endif
 196 #endif
 197
 198 #ifdef CONFIG_FEC_MXC
 199 static int setup_fec(int fec_id)
 200 {
 201         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 202         int ret;
 203
 204         if (fec_id == 0) {
 205                 /*
 206                  * Use 50M anatop loopback REF_CLK1 for ENET1,
 207                  * clear gpr1[13], set gpr1[17].
 208                  */
 209                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 210                                 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 211         } else {
 212                 /*
 213                  * Use 50M anatop loopback REF_CLK2 for ENET2,
 214                  * clear gpr1[14], set gpr1[18].
 215                  */
 216                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 217                                 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 218         }
 219
 220         ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
 221         if (ret)
 222                 return ret;
 223
 224         enable_enet_clk(1);
 225
 226         return 0;
 227 }
 228
 229 int board_phy_config(struct phy_device *phydev)
 230 {
 231         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
 232
 233         if (phydev->drv->config)
 234                 phydev->drv->config(phydev);
 235
 236         return 0;
 237 }
 238 #endif
 239
 240 #ifdef CONFIG_DM_VIDEO
 241 static iomux_v3_cfg_t const lcd_pads[] = {
 242         /* Use GPIO for Brightness adjustment, duty cycle = period. */
 243         MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 244 };
 245
 246 static int setup_lcd(void)
 247 {
 248         enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
 249
 250         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 251
 252         /* Reset the LCD */
 253         gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
 254         gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
 255         udelay(500);
 256         gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
 257
 258         /* Set Brightness to high */
 259         gpio_request(IMX_GPIO_NR(1, 8), "backlight");
 260         gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
 261
 262         return 0;
 263 }
 264 #else
 265 static inline int setup_lcd(void) { return 0; }
 266 #endif
 267
 268 int board_early_init_f(void)
 269 {
 270         setup_iomux_uart();
 271
 272         return 0;
 273 }
 274
 275 int board_init(void)
 276 {
 277         /* Address of boot parameters */
 278         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 279
 280 #ifdef  CONFIG_FEC_MXC
 281         setup_fec(CONFIG_FEC_ENET_DEV);
 282 #endif
 283
 284 #ifdef CONFIG_USB_EHCI_MX6
 285 #ifndef CONFIG_DM_USB
 286         setup_usb();
 287 #endif
 288 #endif
 289
 290 #ifdef CONFIG_FSL_QSPI
 291         board_qspi_init();
 292 #endif
 293
 294         return 0;
 295 }
 296
 297 #ifdef CONFIG_CMD_BMODE
 298 static const struct boot_mode board_boot_modes[] = {
 299         /* 4 bit bus width */
 300         {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
 301         {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 302         {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
 303         {NULL,   0},
 304 };
 305 #endif
 306
 307 int board_late_init(void)
 308 {
 309 #ifdef CONFIG_CMD_BMODE
 310         add_board_boot_modes(board_boot_modes);
 311 #endif
 312
 313 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 314         env_set("board_name", "EVK");
 315
 316         if (is_mx6ul_9x9_evk())
 317                 env_set("board_rev", "9X9");
 318         else
 319                 env_set("board_rev", "14X14");
 320 #endif
 321
 322         setup_lcd();
 323
 324         return 0;
 325 }
 326
 327 int checkboard(void)
 328 {
 329         if (is_mx6ul_9x9_evk())
 330                 puts("Board: MX6UL 9x9 EVK\n");
 331         else
 332                 puts("Board: MX6UL 14x14 EVK\n");
 333
 334         return 0;
 335 }
 336
 337 /*
 338  * Backlight off and reset LCD before OS handover
 339  */
 340 void board_preboot_os(void)
 341 {
 342         gpio_set_value(IMX_GPIO_NR(1, 8), 0);
 343         gpio_set_value(IMX_GPIO_NR(5, 9), 0);
 344 }
 345
 346 #ifdef CONFIG_SPL_BUILD
 347 #include <linux/libfdt.h>
 348 #include <spl.h>
 349 #include <asm/arch/mx6-ddr.h>
 350
 351
 352 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 353         .grp_addds = 0x00000030,
 354         .grp_ddrmode_ctl = 0x00020000,
 355         .grp_b0ds = 0x00000030,
 356         .grp_ctlds = 0x00000030,
 357         .grp_b1ds = 0x00000030,
 358         .grp_ddrpke = 0x00000000,
 359         .grp_ddrmode = 0x00020000,
 360 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
 361         .grp_ddr_type = 0x00080000,
 362 #else
 363         .grp_ddr_type = 0x000c0000,
 364 #endif
 365 };
 366
 367 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
 368 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 369         .dram_dqm0 = 0x00000030,
 370         .dram_dqm1 = 0x00000030,
 371         .dram_ras = 0x00000030,
 372         .dram_cas = 0x00000030,
 373         .dram_odt0 = 0x00000000,
 374         .dram_odt1 = 0x00000000,
 375         .dram_sdba2 = 0x00000000,
 376         .dram_sdclk_0 = 0x00000030,
 377         .dram_sdqs0 = 0x00003030,
 378         .dram_sdqs1 = 0x00003030,
 379         .dram_reset = 0x00000030,
 380 };
 381
 382 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 383         .p0_mpwldectrl0 = 0x00000000,
 384         .p0_mpdgctrl0 = 0x20000000,
 385         .p0_mprddlctl = 0x4040484f,
 386         .p0_mpwrdlctl = 0x40405247,
 387         .mpzqlp2ctl = 0x1b4700c7,
 388 };
 389
 390 static struct mx6_lpddr2_cfg mem_ddr = {
 391         .mem_speed = 800,
 392         .density = 2,
 393         .width = 16,
 394         .banks = 4,
 395         .rowaddr = 14,
 396         .coladdr = 10,
 397         .trcd_lp = 1500,
 398         .trppb_lp = 1500,
 399         .trpab_lp = 2000,
 400         .trasmin = 4250,
 401 };
 402
 403 struct mx6_ddr_sysinfo ddr_sysinfo = {
 404         .dsize = 0,
 405         .cs_density = 18,
 406         .ncs = 1,
 407         .cs1_mirror = 0,
 408         .walat = 0,
 409         .ralat = 5,
 410         .mif3_mode = 3,
 411         .bi_on = 1,
 412         .rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
 413         .rtt_nom = 0,
 414         .sde_to_rst = 0,    /* LPDDR2 does not need this field */
 415         .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 416         .ddr_type = DDR_TYPE_LPDDR2,
 417         .refsel = 0,    /* Refresh cycles at 64KHz */
 418         .refr = 3,      /* 4 refresh commands per refresh cycle */
 419 };
 420
 421 #else
 422 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 423         .dram_dqm0 = 0x00000030,
 424         .dram_dqm1 = 0x00000030,
 425         .dram_ras = 0x00000030,
 426         .dram_cas = 0x00000030,
 427         .dram_odt0 = 0x00000030,
 428         .dram_odt1 = 0x00000030,
 429         .dram_sdba2 = 0x00000000,
 430         .dram_sdclk_0 = 0x00000030,
 431         .dram_sdqs0 = 0x00000030,
 432         .dram_sdqs1 = 0x00000030,
 433         .dram_reset = 0x00000030,
 434 };
 435
 436 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 437         .p0_mpwldectrl0 = 0x00000000,
 438         .p0_mpdgctrl0 = 0x41570155,
 439         .p0_mprddlctl = 0x4040474A,
 440         .p0_mpwrdlctl = 0x40405550,
 441 };
 442
 443 struct mx6_ddr_sysinfo ddr_sysinfo = {
 444         .dsize = 0,
 445         .cs_density = 20,
 446         .ncs = 1,
 447         .cs1_mirror = 0,
 448         .rtt_wr = 2,
 449         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 450         .walat = 0,             /* Write additional latency */
 451         .ralat = 5,             /* Read additional latency */
 452         .mif3_mode = 3,         /* Command prediction working mode */
 453         .bi_on = 1,             /* Bank interleaving enabled */
 454         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 455         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 456         .ddr_type = DDR_TYPE_DDR3,
 457         .refsel = 0,    /* Refresh cycles at 64KHz */
 458         .refr = 1,      /* 2 refresh commands per refresh cycle */
 459 };
 460
 461 static struct mx6_ddr3_cfg mem_ddr = {
 462         .mem_speed = 800,
 463         .density = 4,
 464         .width = 16,
 465         .banks = 8,
 466         .rowaddr = 15,
 467         .coladdr = 10,
 468         .pagesz = 2,
 469         .trcd = 1375,
 470         .trcmin = 4875,
 471         .trasmin = 3500,
 472 };
 473 #endif
 474
 475 static void ccgr_init(void)
 476 {
 477         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 478
 479         writel(0xFFFFFFFF, &ccm->CCGR0);
 480         writel(0xFFFFFFFF, &ccm->CCGR1);
 481         writel(0xFFFFFFFF, &ccm->CCGR2);
 482         writel(0xFFFFFFFF, &ccm->CCGR3);
 483         writel(0xFFFFFFFF, &ccm->CCGR4);
 484         writel(0xFFFFFFFF, &ccm->CCGR5);
 485         writel(0xFFFFFFFF, &ccm->CCGR6);
 486         writel(0xFFFFFFFF, &ccm->CCGR7);
 487 }
 488
 489 static void spl_dram_init(void)
 490 {
 491         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 492         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 493 }
 494
 495 void board_init_f(ulong dummy)
 496 {
 497         ccgr_init();
 498
 499         /* setup AIPS and disable watchdog */
 500         arch_cpu_init();
 501
 502         /* iomux and setup of i2c */
 503         board_early_init_f();
 504
 505         /* setup GP timer */
 506         timer_init();
 507
 508         /* UART clocks enabled and gd valid - init serial console */
 509         preloader_console_init();
 510
 511         /* DDR initialization */
 512         spl_dram_init();
 513
 514         /* Clear the BSS. */
 515         memset(__bss_start, 0, __bss_end - __bss_start);
 516
 517         /* load/boot image from boot device */
 518         board_init_r(NULL, 0);
 519 }
 520 #endif