1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
6 #include <asm/arch/clock.h>
7 #include <asm/arch/iomux.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/crm_regs.h>
10 #include <asm/arch/mx6ul_pins.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/mxc_i2c.h>
20 #include <fsl_esdhc_imx.h>
23 #include <linux/sizes.h>
26 #include <power/pmic.h>
27 #include <power/pfuze3000_pmic.h>
28 #include "../common/pfuze.h"
30 #include <usb/ehci-ci.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
43 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
44 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
51 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
52 PAD_CTL_SPEED_HIGH | \
53 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
55 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
56 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
58 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
59 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
61 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
63 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
64 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
65 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
68 int power_init_board(void)
71 int ret, dev_id, rev_id;
74 ret = pmic_get("pfuze3000", &dev);
80 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
81 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
82 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
84 /* disable Low Power Mode during standby mode */
85 reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
87 pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
89 /* SW1B step ramp up time from 2us to 4us/25mV */
90 pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
92 /* SW1B mode to APS/PFM */
93 pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
95 /* SW1B standby voltage set to 0.975V */
96 pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
104 gd->ram_size = imx_ddr_size();
109 static iomux_v3_cfg_t const uart1_pads[] = {
110 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
111 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
114 #ifndef CONFIG_SPL_BUILD
115 static iomux_v3_cfg_t const usdhc1_pads[] = {
116 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
128 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
133 * mx6ul_14x14_evk board default supports sd card. If want to use
134 * EMMC, need to do board rework for sd2.
135 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
136 * emmc, need to define this macro.
138 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
139 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
140 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
157 static iomux_v3_cfg_t const usdhc2_pads[] = {
158 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
167 * The evk board uses DAT3 to detect CD card plugin,
168 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
170 static iomux_v3_cfg_t const usdhc2_cd_pad =
171 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
173 static iomux_v3_cfg_t const usdhc2_dat3_pad =
174 MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
175 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
178 static void setup_iomux_uart(void)
180 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
183 #ifdef CONFIG_FSL_QSPI
184 static int board_qspi_init(void)
193 #ifdef CONFIG_FSL_ESDHC_IMX
194 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
195 {USDHC1_BASE_ADDR, 0, 4},
196 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
197 {USDHC2_BASE_ADDR, 0, 8},
199 {USDHC2_BASE_ADDR, 0, 4},
203 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
204 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
205 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
206 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
208 int board_mmc_getcd(struct mmc *mmc)
210 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
213 switch (cfg->esdhc_base) {
214 case USDHC1_BASE_ADDR:
215 ret = !gpio_get_value(USDHC1_CD_GPIO);
217 case USDHC2_BASE_ADDR:
218 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
221 imx_iomux_v3_setup_pad(usdhc2_cd_pad);
222 gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
223 gpio_direction_input(USDHC2_CD_GPIO);
226 * Since it is the DAT3 pin, this pin is pulled to
227 * low voltage if no card
229 ret = gpio_get_value(USDHC2_CD_GPIO);
231 imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
239 int board_mmc_init(bd_t *bis)
241 #ifdef CONFIG_SPL_BUILD
242 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
243 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
244 ARRAY_SIZE(usdhc2_emmc_pads));
246 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
248 gpio_direction_output(USDHC2_PWR_GPIO, 0);
250 gpio_direction_output(USDHC2_PWR_GPIO, 1);
251 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
252 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
257 * According to the board_mmc_init() the following map is done:
258 * (U-Boot device node) (Physical Port)
262 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
265 imx_iomux_v3_setup_multiple_pads(
266 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
267 gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
268 gpio_direction_input(USDHC1_CD_GPIO);
269 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
271 gpio_direction_output(USDHC1_PWR_GPIO, 0);
273 gpio_direction_output(USDHC1_PWR_GPIO, 1);
276 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
277 imx_iomux_v3_setup_multiple_pads(
278 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
280 imx_iomux_v3_setup_multiple_pads(
281 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
283 gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
284 gpio_direction_output(USDHC2_PWR_GPIO, 0);
286 gpio_direction_output(USDHC2_PWR_GPIO, 1);
287 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
290 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
294 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
296 printf("Warning: failed to initialize mmc dev %d\n", i);
305 #ifdef CONFIG_USB_EHCI_MX6
306 #ifndef CONFIG_DM_USB
308 #define USB_OTHERREGS_OFFSET 0x800
309 #define UCTRL_PWR_POL (1 << 9)
311 static iomux_v3_cfg_t const usb_otg_pads[] = {
312 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
315 /* At default the 3v3 enables the MIC2026 for VBUS power */
316 static void setup_usb(void)
318 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
319 ARRAY_SIZE(usb_otg_pads));
322 int board_usb_phy_mode(int port)
325 return USB_INIT_HOST;
327 return usb_phy_mode(port);
330 int board_ehci_hcd_init(int port)
337 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
340 /* Set Power polarity */
341 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
348 #ifdef CONFIG_FEC_MXC
350 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
351 * be used for ENET1 or ENET2, cannot be used for both.
353 static iomux_v3_cfg_t const fec1_pads[] = {
354 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
355 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
356 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
357 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
358 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
359 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
360 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
361 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
362 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
363 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
366 static iomux_v3_cfg_t const fec2_pads[] = {
367 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
368 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
370 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
371 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
372 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
373 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
375 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
376 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
377 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
378 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
381 static void setup_iomux_fec(int fec_id)
384 imx_iomux_v3_setup_multiple_pads(fec1_pads,
385 ARRAY_SIZE(fec1_pads));
387 imx_iomux_v3_setup_multiple_pads(fec2_pads,
388 ARRAY_SIZE(fec2_pads));
391 int board_eth_init(bd_t *bis)
393 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
395 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
396 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
399 static int setup_fec(int fec_id)
401 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
406 * Use 50M anatop loopback REF_CLK1 for ENET1,
407 * clear gpr1[13], set gpr1[17].
409 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
410 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
413 * Use 50M anatop loopback REF_CLK2 for ENET2,
414 * clear gpr1[14], set gpr1[18].
416 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
417 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
420 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
429 int board_phy_config(struct phy_device *phydev)
431 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
433 if (phydev->drv->config)
434 phydev->drv->config(phydev);
440 #ifdef CONFIG_VIDEO_MXS
441 static iomux_v3_cfg_t const lcd_pads[] = {
442 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
443 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
444 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
445 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
446 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
447 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
448 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
449 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
450 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
451 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
452 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
453 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
454 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
455 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
456 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
457 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
458 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
459 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
460 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
461 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
462 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
463 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
464 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
465 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
466 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
467 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
468 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
469 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
472 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
474 /* Use GPIO for Brightness adjustment, duty cycle = period. */
475 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
478 static int setup_lcd(void)
480 enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
482 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
485 gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
486 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
488 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
490 /* Set Brightness to high */
491 gpio_request(IMX_GPIO_NR(1, 8), "backlight");
492 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
498 int board_early_init_f(void)
507 /* Address of boot parameters */
508 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
510 #ifdef CONFIG_FEC_MXC
511 setup_fec(CONFIG_FEC_ENET_DEV);
514 #ifdef CONFIG_USB_EHCI_MX6
515 #ifndef CONFIG_DM_USB
520 #ifdef CONFIG_FSL_QSPI
524 #ifdef CONFIG_VIDEO_MXS
531 #ifdef CONFIG_CMD_BMODE
532 static const struct boot_mode board_boot_modes[] = {
533 /* 4 bit bus width */
534 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
535 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
536 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
541 int board_late_init(void)
543 #ifdef CONFIG_CMD_BMODE
544 add_board_boot_modes(board_boot_modes);
547 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
548 env_set("board_name", "EVK");
550 if (is_mx6ul_9x9_evk())
551 env_set("board_rev", "9X9");
553 env_set("board_rev", "14X14");
561 if (is_mx6ul_9x9_evk())
562 puts("Board: MX6UL 9x9 EVK\n");
564 puts("Board: MX6UL 14x14 EVK\n");
569 #ifdef CONFIG_SPL_BUILD
570 #include <linux/libfdt.h>
572 #include <asm/arch/mx6-ddr.h>
575 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
576 .grp_addds = 0x00000030,
577 .grp_ddrmode_ctl = 0x00020000,
578 .grp_b0ds = 0x00000030,
579 .grp_ctlds = 0x00000030,
580 .grp_b1ds = 0x00000030,
581 .grp_ddrpke = 0x00000000,
582 .grp_ddrmode = 0x00020000,
583 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
584 .grp_ddr_type = 0x00080000,
586 .grp_ddr_type = 0x000c0000,
590 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
591 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
592 .dram_dqm0 = 0x00000030,
593 .dram_dqm1 = 0x00000030,
594 .dram_ras = 0x00000030,
595 .dram_cas = 0x00000030,
596 .dram_odt0 = 0x00000000,
597 .dram_odt1 = 0x00000000,
598 .dram_sdba2 = 0x00000000,
599 .dram_sdclk_0 = 0x00000030,
600 .dram_sdqs0 = 0x00003030,
601 .dram_sdqs1 = 0x00003030,
602 .dram_reset = 0x00000030,
605 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
606 .p0_mpwldectrl0 = 0x00000000,
607 .p0_mpdgctrl0 = 0x20000000,
608 .p0_mprddlctl = 0x4040484f,
609 .p0_mpwrdlctl = 0x40405247,
610 .mpzqlp2ctl = 0x1b4700c7,
613 static struct mx6_lpddr2_cfg mem_ddr = {
626 struct mx6_ddr_sysinfo ddr_sysinfo = {
635 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
637 .sde_to_rst = 0, /* LPDDR2 does not need this field */
638 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
639 .ddr_type = DDR_TYPE_LPDDR2,
640 .refsel = 0, /* Refresh cycles at 64KHz */
641 .refr = 3, /* 4 refresh commands per refresh cycle */
645 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
646 .dram_dqm0 = 0x00000030,
647 .dram_dqm1 = 0x00000030,
648 .dram_ras = 0x00000030,
649 .dram_cas = 0x00000030,
650 .dram_odt0 = 0x00000030,
651 .dram_odt1 = 0x00000030,
652 .dram_sdba2 = 0x00000000,
653 .dram_sdclk_0 = 0x00000030,
654 .dram_sdqs0 = 0x00000030,
655 .dram_sdqs1 = 0x00000030,
656 .dram_reset = 0x00000030,
659 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
660 .p0_mpwldectrl0 = 0x00000000,
661 .p0_mpdgctrl0 = 0x41570155,
662 .p0_mprddlctl = 0x4040474A,
663 .p0_mpwrdlctl = 0x40405550,
666 struct mx6_ddr_sysinfo ddr_sysinfo = {
672 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
673 .walat = 0, /* Write additional latency */
674 .ralat = 5, /* Read additional latency */
675 .mif3_mode = 3, /* Command prediction working mode */
676 .bi_on = 1, /* Bank interleaving enabled */
677 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
678 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
679 .ddr_type = DDR_TYPE_DDR3,
680 .refsel = 0, /* Refresh cycles at 64KHz */
681 .refr = 1, /* 2 refresh commands per refresh cycle */
684 static struct mx6_ddr3_cfg mem_ddr = {
698 static void ccgr_init(void)
700 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
702 writel(0xFFFFFFFF, &ccm->CCGR0);
703 writel(0xFFFFFFFF, &ccm->CCGR1);
704 writel(0xFFFFFFFF, &ccm->CCGR2);
705 writel(0xFFFFFFFF, &ccm->CCGR3);
706 writel(0xFFFFFFFF, &ccm->CCGR4);
707 writel(0xFFFFFFFF, &ccm->CCGR5);
708 writel(0xFFFFFFFF, &ccm->CCGR6);
709 writel(0xFFFFFFFF, &ccm->CCGR7);
712 static void spl_dram_init(void)
714 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
715 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
718 void board_init_f(ulong dummy)
722 /* setup AIPS and disable watchdog */
725 /* iomux and setup of i2c */
726 board_early_init_f();
731 /* UART clocks enabled and gd valid - init serial console */
732 preloader_console_init();
734 /* DDR initialization */
738 memset(__bss_start, 0, __bss_end - __bss_start);
740 /* load/boot image from boot device */
741 board_init_r(NULL, 0);