board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <init.h>
   7 #include <net.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/iomux.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/mx6ul_pins.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/global_data.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/boot_mode.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20 #include <asm/io.h>
  21 #include <common.h>
  22 #include <env.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <i2c.h>
  25 #include <miiphy.h>
  26 #include <linux/delay.h>
  27 #include <linux/sizes.h>
  28 #include <mmc.h>
  29 #include <netdev.h>
  30 #include <power/pmic.h>
  31 #include <power/pfuze3000_pmic.h>
  32 #include "../common/pfuze.h"
  33 #include <usb.h>
  34 #include <usb/ehci-ci.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  39         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  40         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  43         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  44         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  45         PAD_CTL_ODE)
  46
  47 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  48         PAD_CTL_SPEED_HIGH   |                                  \
  49         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  50
  51 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  52         PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  53
  54 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  55         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  56
  57 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  58
  59 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  60         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  61         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  62
  63 #ifdef CONFIG_DM_PMIC
  64 int power_init_board(void)
  65 {
  66         struct udevice *dev;
  67         int ret, dev_id, rev_id;
  68         unsigned int reg;
  69
  70         ret = pmic_get("pfuze3000", &dev);
  71         if (ret == -ENODEV)
  72                 return 0;
  73         if (ret != 0)
  74                 return ret;
  75
  76         dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  77         rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  78         printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  79
  80         /* disable Low Power Mode during standby mode */
  81         reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
  82         reg |= 0x1;
  83         pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
  84
  85         /* SW1B step ramp up time from 2us to 4us/25mV */
  86         pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
  87
  88         /* SW1B mode to APS/PFM */
  89         pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
  90
  91         /* SW1B standby voltage set to 0.975V */
  92         pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
  93
  94         return 0;
  95 }
  96 #endif
  97
  98 int dram_init(void)
  99 {
 100         gd->ram_size = imx_ddr_size();
 101
 102         return 0;
 103 }
 104
 105 static iomux_v3_cfg_t const uart1_pads[] = {
 106         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 107         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 108 };
 109
 110
 111 static void setup_iomux_uart(void)
 112 {
 113         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 114 }
 115
 116 #ifdef CONFIG_FSL_QSPI
 117 static int board_qspi_init(void)
 118 {
 119         /* Set the clock */
 120         enable_qspi_clk(0);
 121
 122         return 0;
 123 }
 124 #endif
 125
 126 #ifdef CONFIG_SPL_BUILD
 127
 128 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 129         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 130         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 131
 132 static iomux_v3_cfg_t const usdhc2_pads[] = {
 133         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139 };
 140
 141 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 142         {USDHC2_BASE_ADDR, 0, 4},
 143 };
 144
 145 int board_mmc_getcd(struct mmc *mmc)
 146 {
 147         return 1;
 148 }
 149
 150 int board_mmc_init(struct bd_info *bis)
 151 {
 152         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 153         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 154         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 155 }
 156 #endif
 157
 158 #ifdef CONFIG_USB_EHCI_MX6
 159 #ifndef CONFIG_DM_USB
 160
 161 #define USB_OTHERREGS_OFFSET    0x800
 162 #define UCTRL_PWR_POL           (1 << 9)
 163
 164 static iomux_v3_cfg_t const usb_otg_pads[] = {
 165         MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
 166 };
 167
 168 /* At default the 3v3 enables the MIC2026 for VBUS power */
 169 static void setup_usb(void)
 170 {
 171         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 172                                          ARRAY_SIZE(usb_otg_pads));
 173 }
 174
 175 int board_usb_phy_mode(int port)
 176 {
 177         if (port == 1)
 178                 return USB_INIT_HOST;
 179         else
 180                 return usb_phy_mode(port);
 181 }
 182
 183 int board_ehci_hcd_init(int port)
 184 {
 185         u32 *usbnc_usb_ctrl;
 186
 187         if (port > 1)
 188                 return -EINVAL;
 189
 190         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 191                                  port * 4);
 192
 193         /* Set Power polarity */
 194         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 195
 196         return 0;
 197 }
 198 #endif
 199 #endif
 200
 201 #ifdef CONFIG_FEC_MXC
 202 static int setup_fec(int fec_id)
 203 {
 204         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 205         int ret;
 206
 207         if (fec_id == 0) {
 208                 /*
 209                  * Use 50M anatop loopback REF_CLK1 for ENET1,
 210                  * clear gpr1[13], set gpr1[17].
 211                  */
 212                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 213                                 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 214         } else {
 215                 /*
 216                  * Use 50M anatop loopback REF_CLK2 for ENET2,
 217                  * clear gpr1[14], set gpr1[18].
 218                  */
 219                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 220                                 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 221         }
 222
 223         ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
 224         if (ret)
 225                 return ret;
 226
 227         enable_enet_clk(1);
 228
 229         return 0;
 230 }
 231
 232 int board_phy_config(struct phy_device *phydev)
 233 {
 234         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
 235
 236         if (phydev->drv->config)
 237                 phydev->drv->config(phydev);
 238
 239         return 0;
 240 }
 241 #endif
 242
 243 #ifdef CONFIG_DM_VIDEO
 244 static iomux_v3_cfg_t const lcd_pads[] = {
 245         /* Use GPIO for Brightness adjustment, duty cycle = period. */
 246         MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 247 };
 248
 249 static int setup_lcd(void)
 250 {
 251         enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
 252
 253         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 254
 255         /* Reset the LCD */
 256         gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
 257         gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
 258         udelay(500);
 259         gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
 260
 261         /* Set Brightness to high */
 262         gpio_request(IMX_GPIO_NR(1, 8), "backlight");
 263         gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
 264
 265         return 0;
 266 }
 267 #else
 268 static inline int setup_lcd(void) { return 0; }
 269 #endif
 270
 271 int board_early_init_f(void)
 272 {
 273         setup_iomux_uart();
 274
 275         return 0;
 276 }
 277
 278 int board_init(void)
 279 {
 280         /* Address of boot parameters */
 281         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 282
 283 #ifdef  CONFIG_FEC_MXC
 284         setup_fec(CONFIG_FEC_ENET_DEV);
 285 #endif
 286
 287 #ifdef CONFIG_USB_EHCI_MX6
 288 #ifndef CONFIG_DM_USB
 289         setup_usb();
 290 #endif
 291 #endif
 292
 293 #ifdef CONFIG_FSL_QSPI
 294         board_qspi_init();
 295 #endif
 296
 297         return 0;
 298 }
 299
 300 #ifdef CONFIG_CMD_BMODE
 301 static const struct boot_mode board_boot_modes[] = {
 302         /* 4 bit bus width */
 303         {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
 304         {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 305         {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
 306         {NULL,   0},
 307 };
 308 #endif
 309
 310 int board_late_init(void)
 311 {
 312 #ifdef CONFIG_CMD_BMODE
 313         add_board_boot_modes(board_boot_modes);
 314 #endif
 315
 316 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 317         env_set("board_name", "EVK");
 318
 319         if (is_mx6ul_9x9_evk())
 320                 env_set("board_rev", "9X9");
 321         else
 322                 env_set("board_rev", "14X14");
 323 #endif
 324
 325         setup_lcd();
 326
 327         return 0;
 328 }
 329
 330 int checkboard(void)
 331 {
 332         if (is_mx6ul_9x9_evk())
 333                 puts("Board: MX6UL 9x9 EVK\n");
 334         else
 335                 puts("Board: MX6UL 14x14 EVK\n");
 336
 337         return 0;
 338 }
 339
 340 /*
 341  * Backlight off and reset LCD before OS handover
 342  */
 343 void board_preboot_os(void)
 344 {
 345         gpio_set_value(IMX_GPIO_NR(1, 8), 0);
 346         gpio_set_value(IMX_GPIO_NR(5, 9), 0);
 347 }
 348
 349 #ifdef CONFIG_SPL_BUILD
 350 #include <linux/libfdt.h>
 351 #include <spl.h>
 352 #include <asm/arch/mx6-ddr.h>
 353
 354
 355 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 356         .grp_addds = 0x00000030,
 357         .grp_ddrmode_ctl = 0x00020000,
 358         .grp_b0ds = 0x00000030,
 359         .grp_ctlds = 0x00000030,
 360         .grp_b1ds = 0x00000030,
 361         .grp_ddrpke = 0x00000000,
 362         .grp_ddrmode = 0x00020000,
 363 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
 364         .grp_ddr_type = 0x00080000,
 365 #else
 366         .grp_ddr_type = 0x000c0000,
 367 #endif
 368 };
 369
 370 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
 371 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 372         .dram_dqm0 = 0x00000030,
 373         .dram_dqm1 = 0x00000030,
 374         .dram_ras = 0x00000030,
 375         .dram_cas = 0x00000030,
 376         .dram_odt0 = 0x00000000,
 377         .dram_odt1 = 0x00000000,
 378         .dram_sdba2 = 0x00000000,
 379         .dram_sdclk_0 = 0x00000030,
 380         .dram_sdqs0 = 0x00003030,
 381         .dram_sdqs1 = 0x00003030,
 382         .dram_reset = 0x00000030,
 383 };
 384
 385 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 386         .p0_mpwldectrl0 = 0x00000000,
 387         .p0_mpdgctrl0 = 0x20000000,
 388         .p0_mprddlctl = 0x4040484f,
 389         .p0_mpwrdlctl = 0x40405247,
 390         .mpzqlp2ctl = 0x1b4700c7,
 391 };
 392
 393 static struct mx6_lpddr2_cfg mem_ddr = {
 394         .mem_speed = 800,
 395         .density = 2,
 396         .width = 16,
 397         .banks = 4,
 398         .rowaddr = 14,
 399         .coladdr = 10,
 400         .trcd_lp = 1500,
 401         .trppb_lp = 1500,
 402         .trpab_lp = 2000,
 403         .trasmin = 4250,
 404 };
 405
 406 struct mx6_ddr_sysinfo ddr_sysinfo = {
 407         .dsize = 0,
 408         .cs_density = 18,
 409         .ncs = 1,
 410         .cs1_mirror = 0,
 411         .walat = 0,
 412         .ralat = 5,
 413         .mif3_mode = 3,
 414         .bi_on = 1,
 415         .rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
 416         .rtt_nom = 0,
 417         .sde_to_rst = 0,    /* LPDDR2 does not need this field */
 418         .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 419         .ddr_type = DDR_TYPE_LPDDR2,
 420         .refsel = 0,    /* Refresh cycles at 64KHz */
 421         .refr = 3,      /* 4 refresh commands per refresh cycle */
 422 };
 423
 424 #else
 425 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 426         .dram_dqm0 = 0x00000030,
 427         .dram_dqm1 = 0x00000030,
 428         .dram_ras = 0x00000030,
 429         .dram_cas = 0x00000030,
 430         .dram_odt0 = 0x00000030,
 431         .dram_odt1 = 0x00000030,
 432         .dram_sdba2 = 0x00000000,
 433         .dram_sdclk_0 = 0x00000030,
 434         .dram_sdqs0 = 0x00000030,
 435         .dram_sdqs1 = 0x00000030,
 436         .dram_reset = 0x00000030,
 437 };
 438
 439 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 440         .p0_mpwldectrl0 = 0x00000000,
 441         .p0_mpdgctrl0 = 0x41570155,
 442         .p0_mprddlctl = 0x4040474A,
 443         .p0_mpwrdlctl = 0x40405550,
 444 };
 445
 446 struct mx6_ddr_sysinfo ddr_sysinfo = {
 447         .dsize = 0,
 448         .cs_density = 20,
 449         .ncs = 1,
 450         .cs1_mirror = 0,
 451         .rtt_wr = 2,
 452         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 453         .walat = 0,             /* Write additional latency */
 454         .ralat = 5,             /* Read additional latency */
 455         .mif3_mode = 3,         /* Command prediction working mode */
 456         .bi_on = 1,             /* Bank interleaving enabled */
 457         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 458         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 459         .ddr_type = DDR_TYPE_DDR3,
 460         .refsel = 0,    /* Refresh cycles at 64KHz */
 461         .refr = 1,      /* 2 refresh commands per refresh cycle */
 462 };
 463
 464 static struct mx6_ddr3_cfg mem_ddr = {
 465         .mem_speed = 800,
 466         .density = 4,
 467         .width = 16,
 468         .banks = 8,
 469         .rowaddr = 15,
 470         .coladdr = 10,
 471         .pagesz = 2,
 472         .trcd = 1375,
 473         .trcmin = 4875,
 474         .trasmin = 3500,
 475 };
 476 #endif
 477
 478 static void ccgr_init(void)
 479 {
 480         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 481
 482         writel(0xFFFFFFFF, &ccm->CCGR0);
 483         writel(0xFFFFFFFF, &ccm->CCGR1);
 484         writel(0xFFFFFFFF, &ccm->CCGR2);
 485         writel(0xFFFFFFFF, &ccm->CCGR3);
 486         writel(0xFFFFFFFF, &ccm->CCGR4);
 487         writel(0xFFFFFFFF, &ccm->CCGR5);
 488         writel(0xFFFFFFFF, &ccm->CCGR6);
 489         writel(0xFFFFFFFF, &ccm->CCGR7);
 490 }
 491
 492 static void spl_dram_init(void)
 493 {
 494         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 495         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 496 }
 497
 498 void board_init_f(ulong dummy)
 499 {
 500         ccgr_init();
 501
 502         /* setup AIPS and disable watchdog */
 503         arch_cpu_init();
 504
 505         /* iomux and setup of i2c */
 506         board_early_init_f();
 507
 508         /* setup GP timer */
 509         timer_init();
 510
 511         /* UART clocks enabled and gd valid - init serial console */
 512         preloader_console_init();
 513
 514         /* DDR initialization */
 515         spl_dram_init();
 516
 517         /* Clear the BSS. */
 518         memset(__bss_start, 0, __bss_end - __bss_start);
 519
 520         /* load/boot image from boot device */
 521         board_init_r(NULL, 0);
 522 }
 523 #endif