1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6ul_pins.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/mxc_i2c.h>
21 #include <fsl_esdhc_imx.h>
24 #include <linux/sizes.h>
27 #include <power/pmic.h>
28 #include <power/pfuze3000_pmic.h>
29 #include "../common/pfuze.h"
31 #include <usb/ehci-ci.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
36 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
37 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
41 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
45 PAD_CTL_SPEED_HIGH | \
46 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
48 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
49 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
51 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
52 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
54 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
56 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
57 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
58 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
61 int power_init_board(void)
64 int ret, dev_id, rev_id;
67 ret = pmic_get("pfuze3000", &dev);
73 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
74 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
75 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
77 /* disable Low Power Mode during standby mode */
78 reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
80 pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
82 /* SW1B step ramp up time from 2us to 4us/25mV */
83 pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
85 /* SW1B mode to APS/PFM */
86 pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
88 /* SW1B standby voltage set to 0.975V */
89 pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
97 gd->ram_size = imx_ddr_size();
102 static iomux_v3_cfg_t const uart1_pads[] = {
103 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
104 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
108 static void setup_iomux_uart(void)
110 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
113 #ifdef CONFIG_FSL_QSPI
114 static int board_qspi_init(void)
123 #ifdef CONFIG_SPL_BUILD
125 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
126 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
127 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
129 static iomux_v3_cfg_t const usdhc2_pads[] = {
130 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
139 {USDHC2_BASE_ADDR, 0, 4},
142 int board_mmc_getcd(struct mmc *mmc)
147 int board_mmc_init(bd_t *bis)
149 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
150 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
151 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
155 #ifdef CONFIG_USB_EHCI_MX6
156 #ifndef CONFIG_DM_USB
158 #define USB_OTHERREGS_OFFSET 0x800
159 #define UCTRL_PWR_POL (1 << 9)
161 static iomux_v3_cfg_t const usb_otg_pads[] = {
162 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
165 /* At default the 3v3 enables the MIC2026 for VBUS power */
166 static void setup_usb(void)
168 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
169 ARRAY_SIZE(usb_otg_pads));
172 int board_usb_phy_mode(int port)
175 return USB_INIT_HOST;
177 return usb_phy_mode(port);
180 int board_ehci_hcd_init(int port)
187 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
190 /* Set Power polarity */
191 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
198 #ifdef CONFIG_FEC_MXC
200 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
201 * be used for ENET1 or ENET2, cannot be used for both.
203 static iomux_v3_cfg_t const fec1_pads[] = {
204 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
205 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
206 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
207 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
208 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
209 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
210 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
211 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
212 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
213 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
216 static iomux_v3_cfg_t const fec2_pads[] = {
217 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
218 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
220 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
221 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
222 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
223 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
225 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
226 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
227 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
228 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
231 static void setup_iomux_fec(int fec_id)
234 imx_iomux_v3_setup_multiple_pads(fec1_pads,
235 ARRAY_SIZE(fec1_pads));
237 imx_iomux_v3_setup_multiple_pads(fec2_pads,
238 ARRAY_SIZE(fec2_pads));
241 int board_eth_init(bd_t *bis)
243 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
245 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
246 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
249 static int setup_fec(int fec_id)
251 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
256 * Use 50M anatop loopback REF_CLK1 for ENET1,
257 * clear gpr1[13], set gpr1[17].
259 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
260 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
263 * Use 50M anatop loopback REF_CLK2 for ENET2,
264 * clear gpr1[14], set gpr1[18].
266 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
267 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
270 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
279 int board_phy_config(struct phy_device *phydev)
281 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
283 if (phydev->drv->config)
284 phydev->drv->config(phydev);
290 #ifdef CONFIG_DM_VIDEO
291 static iomux_v3_cfg_t const lcd_pads[] = {
292 /* Use GPIO for Brightness adjustment, duty cycle = period. */
293 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
296 static int setup_lcd(void)
298 enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
300 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
303 gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
304 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
306 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
308 /* Set Brightness to high */
309 gpio_request(IMX_GPIO_NR(1, 8), "backlight");
310 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
315 static inline int setup_lcd(void) { return 0; }
318 int board_early_init_f(void)
327 /* Address of boot parameters */
328 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
330 #ifdef CONFIG_FEC_MXC
331 setup_fec(CONFIG_FEC_ENET_DEV);
334 #ifdef CONFIG_USB_EHCI_MX6
335 #ifndef CONFIG_DM_USB
340 #ifdef CONFIG_FSL_QSPI
347 #ifdef CONFIG_CMD_BMODE
348 static const struct boot_mode board_boot_modes[] = {
349 /* 4 bit bus width */
350 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
351 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
352 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
357 int board_late_init(void)
359 #ifdef CONFIG_CMD_BMODE
360 add_board_boot_modes(board_boot_modes);
363 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
364 env_set("board_name", "EVK");
366 if (is_mx6ul_9x9_evk())
367 env_set("board_rev", "9X9");
369 env_set("board_rev", "14X14");
379 if (is_mx6ul_9x9_evk())
380 puts("Board: MX6UL 9x9 EVK\n");
382 puts("Board: MX6UL 14x14 EVK\n");
388 * Backlight off and reset LCD before OS handover
390 void board_preboot_os(void)
392 gpio_set_value(IMX_GPIO_NR(1, 8), 0);
393 gpio_set_value(IMX_GPIO_NR(5, 9), 0);
396 #ifdef CONFIG_SPL_BUILD
397 #include <linux/libfdt.h>
399 #include <asm/arch/mx6-ddr.h>
402 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
403 .grp_addds = 0x00000030,
404 .grp_ddrmode_ctl = 0x00020000,
405 .grp_b0ds = 0x00000030,
406 .grp_ctlds = 0x00000030,
407 .grp_b1ds = 0x00000030,
408 .grp_ddrpke = 0x00000000,
409 .grp_ddrmode = 0x00020000,
410 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
411 .grp_ddr_type = 0x00080000,
413 .grp_ddr_type = 0x000c0000,
417 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
418 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
419 .dram_dqm0 = 0x00000030,
420 .dram_dqm1 = 0x00000030,
421 .dram_ras = 0x00000030,
422 .dram_cas = 0x00000030,
423 .dram_odt0 = 0x00000000,
424 .dram_odt1 = 0x00000000,
425 .dram_sdba2 = 0x00000000,
426 .dram_sdclk_0 = 0x00000030,
427 .dram_sdqs0 = 0x00003030,
428 .dram_sdqs1 = 0x00003030,
429 .dram_reset = 0x00000030,
432 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
433 .p0_mpwldectrl0 = 0x00000000,
434 .p0_mpdgctrl0 = 0x20000000,
435 .p0_mprddlctl = 0x4040484f,
436 .p0_mpwrdlctl = 0x40405247,
437 .mpzqlp2ctl = 0x1b4700c7,
440 static struct mx6_lpddr2_cfg mem_ddr = {
453 struct mx6_ddr_sysinfo ddr_sysinfo = {
462 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
464 .sde_to_rst = 0, /* LPDDR2 does not need this field */
465 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
466 .ddr_type = DDR_TYPE_LPDDR2,
467 .refsel = 0, /* Refresh cycles at 64KHz */
468 .refr = 3, /* 4 refresh commands per refresh cycle */
472 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
473 .dram_dqm0 = 0x00000030,
474 .dram_dqm1 = 0x00000030,
475 .dram_ras = 0x00000030,
476 .dram_cas = 0x00000030,
477 .dram_odt0 = 0x00000030,
478 .dram_odt1 = 0x00000030,
479 .dram_sdba2 = 0x00000000,
480 .dram_sdclk_0 = 0x00000030,
481 .dram_sdqs0 = 0x00000030,
482 .dram_sdqs1 = 0x00000030,
483 .dram_reset = 0x00000030,
486 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
487 .p0_mpwldectrl0 = 0x00000000,
488 .p0_mpdgctrl0 = 0x41570155,
489 .p0_mprddlctl = 0x4040474A,
490 .p0_mpwrdlctl = 0x40405550,
493 struct mx6_ddr_sysinfo ddr_sysinfo = {
499 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
500 .walat = 0, /* Write additional latency */
501 .ralat = 5, /* Read additional latency */
502 .mif3_mode = 3, /* Command prediction working mode */
503 .bi_on = 1, /* Bank interleaving enabled */
504 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
505 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
506 .ddr_type = DDR_TYPE_DDR3,
507 .refsel = 0, /* Refresh cycles at 64KHz */
508 .refr = 1, /* 2 refresh commands per refresh cycle */
511 static struct mx6_ddr3_cfg mem_ddr = {
525 static void ccgr_init(void)
527 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
529 writel(0xFFFFFFFF, &ccm->CCGR0);
530 writel(0xFFFFFFFF, &ccm->CCGR1);
531 writel(0xFFFFFFFF, &ccm->CCGR2);
532 writel(0xFFFFFFFF, &ccm->CCGR3);
533 writel(0xFFFFFFFF, &ccm->CCGR4);
534 writel(0xFFFFFFFF, &ccm->CCGR5);
535 writel(0xFFFFFFFF, &ccm->CCGR6);
536 writel(0xFFFFFFFF, &ccm->CCGR7);
539 static void spl_dram_init(void)
541 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
542 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
545 void board_init_f(ulong dummy)
549 /* setup AIPS and disable watchdog */
552 /* iomux and setup of i2c */
553 board_early_init_f();
558 /* UART clocks enabled and gd valid - init serial console */
559 preloader_console_init();
561 /* DDR initialization */
565 memset(__bss_start, 0, __bss_end - __bss_start);
567 /* load/boot image from boot device */
568 board_init_r(NULL, 0);