board/freescale/mx6slevk/mx6slevk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  */
   7
   8 #include <init.h>
   9 #include <net.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/mx6-ddr.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/global_data.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/io.h>
  22 #include <linux/sizes.h>
  23 #include <common.h>
  24 #include <fsl_esdhc_imx.h>
  25 #include <i2c.h>
  26 #include <mmc.h>
  27 #include <power/pmic.h>
  28 #include <power/pfuze100_pmic.h>
  29 #include "../common/pfuze.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  34         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  35         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  36
  37 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |                    \
  38         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  39         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  42         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  43         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  44
  45 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  46                         PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
  47                         PAD_CTL_DSE_80ohm | PAD_CTL_HYS |       \
  48                         PAD_CTL_SRE_FAST)
  49
  50 #define ETH_PHY_POWER   IMX_GPIO_NR(4, 21)
  51
  52 int dram_init(void)
  53 {
  54         gd->ram_size = imx_ddr_size();
  55
  56         return 0;
  57 }
  58
  59 static iomux_v3_cfg_t const uart1_pads[] = {
  60         MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  61         MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  62 };
  63
  64 #ifdef CONFIG_SPL_BUILD
  65 static iomux_v3_cfg_t const usdhc1_pads[] = {
  66         /* 8 bit SD */
  67         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69         MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70         MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71         MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77
  78         /*CD pin*/
  79         MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  80 };
  81
  82 static iomux_v3_cfg_t const usdhc2_pads[] = {
  83         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89
  90         /*CD pin*/
  91         MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
  92 };
  93
  94 static iomux_v3_cfg_t const usdhc3_pads[] = {
  95         MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101
 102         /*CD pin*/
 103         MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 104 };
 105 #endif
 106
 107 static void setup_iomux_uart(void)
 108 {
 109         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 110 }
 111
 112 int board_mmc_get_env_dev(int devno)
 113 {
 114         return devno;
 115 }
 116
 117 #ifdef CONFIG_DM_PMIC_PFUZE100
 118 int power_init_board(void)
 119 {
 120         struct udevice *dev;
 121         int ret;
 122         u32 dev_id, rev_id, i;
 123         u32 switch_num = 6;
 124         u32 offset = PFUZE100_SW1CMODE;
 125
 126         ret = pmic_get("pfuze100@08", &dev);
 127         if (ret == -ENODEV)
 128                 return 0;
 129
 130         if (ret != 0)
 131                 return ret;
 132
 133         dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
 134         rev_id = pmic_reg_read(dev, PFUZE100_REVID);
 135         printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
 136
 137         /* set SW1AB staby volatage 0.975V */
 138         pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
 139
 140         /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 141         pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
 142
 143         /* set SW1C staby volatage 0.975V */
 144         pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
 145
 146         /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
 147         pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
 148
 149         /* Init mode to APS_PFM */
 150         pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
 151
 152         for (i = 0; i < switch_num - 1; i++)
 153                 pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
 154
 155         return 0;
 156 }
 157 #endif
 158
 159 #ifdef CONFIG_FEC_MXC
 160
 161 static int setup_fec(void)
 162 {
 163         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 164
 165         /* clear gpr1[14], gpr1[18:17] to select anatop clock */
 166         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 167
 168         return enable_fec_anatop_clock(0, ENET_50MHZ);
 169 }
 170 #endif
 171
 172 int board_early_init_f(void)
 173 {
 174         setup_iomux_uart();
 175
 176         return 0;
 177 }
 178
 179 int board_init(void)
 180 {
 181         /* address of boot parameters */
 182         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 183
 184 #ifdef  CONFIG_FEC_MXC
 185         setup_fec();
 186 #endif
 187
 188         return 0;
 189 }
 190
 191 int checkboard(void)
 192 {
 193         puts("Board: MX6SLEVK\n");
 194
 195         return 0;
 196 }
 197
 198 #ifdef CONFIG_SPL_BUILD
 199 #include <spl.h>
 200 #include <linux/libfdt.h>
 201
 202 #define USDHC1_CD_GPIO  IMX_GPIO_NR(4, 7)
 203 #define USDHC2_CD_GPIO  IMX_GPIO_NR(5, 0)
 204 #define USDHC3_CD_GPIO  IMX_GPIO_NR(3, 22)
 205
 206 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 207         {USDHC1_BASE_ADDR},
 208         {USDHC2_BASE_ADDR, 0, 4},
 209         {USDHC3_BASE_ADDR, 0, 4},
 210 };
 211
 212 int board_mmc_getcd(struct mmc *mmc)
 213 {
 214         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 215         int ret = 0;
 216
 217         switch (cfg->esdhc_base) {
 218         case USDHC1_BASE_ADDR:
 219                 gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
 220                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 221                 break;
 222         case USDHC2_BASE_ADDR:
 223                 gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
 224                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 225                 break;
 226         case USDHC3_BASE_ADDR:
 227                 gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
 228                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 229                 break;
 230         }
 231
 232         return ret;
 233 }
 234
 235 int board_mmc_init(struct bd_info *bis)
 236 {
 237         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 238         u32 val;
 239         u32 port;
 240
 241         val = readl(&src_regs->sbmr1);
 242
 243         /* Boot from USDHC */
 244         port = (val >> 11) & 0x3;
 245         switch (port) {
 246         case 0:
 247                 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
 248                                                  ARRAY_SIZE(usdhc1_pads));
 249                 gpio_direction_input(USDHC1_CD_GPIO);
 250                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 251                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 252                 break;
 253         case 1:
 254                 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
 255                                                  ARRAY_SIZE(usdhc2_pads));
 256                 gpio_direction_input(USDHC2_CD_GPIO);
 257                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 258                 usdhc_cfg[0].max_bus_width = 4;
 259                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 260                 break;
 261         case 2:
 262                 imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
 263                                                  ARRAY_SIZE(usdhc3_pads));
 264                 gpio_direction_input(USDHC3_CD_GPIO);
 265                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 266                 usdhc_cfg[0].max_bus_width = 4;
 267                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 268                 break;
 269         }
 270
 271         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 272         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 273 }
 274
 275 const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
 276         .dram_sdqs0 = 0x00003030,
 277         .dram_sdqs1 = 0x00003030,
 278         .dram_sdqs2 = 0x00003030,
 279         .dram_sdqs3 = 0x00003030,
 280         .dram_dqm0 = 0x00000030,
 281         .dram_dqm1 = 0x00000030,
 282         .dram_dqm2 = 0x00000030,
 283         .dram_dqm3 = 0x00000030,
 284         .dram_cas  = 0x00000030,
 285         .dram_ras  = 0x00000030,
 286         .dram_sdclk_0 = 0x00000028,
 287         .dram_reset = 0x00000030,
 288         .dram_sdba2 = 0x00000000,
 289         .dram_odt0 = 0x00000008,
 290         .dram_odt1 = 0x00000008,
 291 };
 292
 293 const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
 294         .grp_b0ds = 0x00000030,
 295         .grp_b1ds = 0x00000030,
 296         .grp_b2ds = 0x00000030,
 297         .grp_b3ds = 0x00000030,
 298         .grp_addds = 0x00000030,
 299         .grp_ctlds = 0x00000030,
 300         .grp_ddrmode_ctl = 0x00020000,
 301         .grp_ddrpke = 0x00000000,
 302         .grp_ddrmode = 0x00020000,
 303         .grp_ddr_type = 0x00080000,
 304 };
 305
 306 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 307         .p0_mpdgctrl0 =  0x20000000,
 308         .p0_mpdgctrl1 =  0x00000000,
 309         .p0_mprddlctl =  0x4241444a,
 310         .p0_mpwrdlctl =  0x3030312b,
 311         .mpzqlp2ctl = 0x1b4700c7,
 312 };
 313
 314 static struct mx6_lpddr2_cfg mem_ddr = {
 315         .mem_speed = 800,
 316         .density = 4,
 317         .width = 32,
 318         .banks = 8,
 319         .rowaddr = 14,
 320         .coladdr = 10,
 321         .trcd_lp = 2000,
 322         .trppb_lp = 2000,
 323         .trpab_lp = 2250,
 324         .trasmin = 4200,
 325 };
 326
 327 static void ccgr_init(void)
 328 {
 329         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 330
 331         writel(0xFFFFFFFF, &ccm->CCGR0);
 332         writel(0xFFFFFFFF, &ccm->CCGR1);
 333         writel(0xFFFFFFFF, &ccm->CCGR2);
 334         writel(0xFFFFFFFF, &ccm->CCGR3);
 335         writel(0xFFFFFFFF, &ccm->CCGR4);
 336         writel(0xFFFFFFFF, &ccm->CCGR5);
 337         writel(0xFFFFFFFF, &ccm->CCGR6);
 338
 339         writel(0x00260324, &ccm->cbcmr);
 340 }
 341
 342 static void spl_dram_init(void)
 343 {
 344         struct mx6_ddr_sysinfo sysinfo = {
 345                 .dsize = mem_ddr.width / 32,
 346                 .cs_density = 20,
 347                 .ncs = 2,
 348                 .cs1_mirror = 0,
 349                 .walat = 0,
 350                 .ralat = 2,
 351                 .mif3_mode = 3,
 352                 .bi_on = 1,
 353                 .rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
 354                 .rtt_nom = 0,
 355                 .sde_to_rst = 0,    /* LPDDR2 does not need this field */
 356                 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 357                 .ddr_type = DDR_TYPE_LPDDR2,
 358                 .refsel = 0,    /* Refresh cycles at 64KHz */
 359                 .refr = 3,      /* 4 refresh commands per refresh cycle */
 360         };
 361         mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 362         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 363 }
 364
 365 void board_init_f(ulong dummy)
 366 {
 367         /* setup AIPS and disable watchdog */
 368         arch_cpu_init();
 369
 370         ccgr_init();
 371
 372         /* iomux and setup of i2c */
 373         board_early_init_f();
 374
 375         /* setup GP timer */
 376         timer_init();
 377
 378         /* UART clocks enabled and gd valid - init serial console */
 379         preloader_console_init();
 380
 381         /* DDR initialization */
 382         spl_dram_init();
 383
 384         /* Clear the BSS. */
 385         memset(__bss_start, 0, __bss_end - __bss_start);
 386
 387         /* load/boot image from boot device */
 388         board_init_r(NULL, 0);
 389 }
 390 #endif