board/freescale/mx6sabresd/mx6sabresd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <asm/mach-imx/spi.h>
  13 #include <linux/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/mxc_i2c.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <miiphy.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <input.h>
  29 #include <power/pmic.h>
  30 #include <power/pfuze100_pmic.h>
  31 #include "../common/pfuze.h"
  32 #include <usb.h>
  33 #include <usb/ehci-ci.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  38         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  39         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  42         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  47
  48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  49                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  50
  51 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  53         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  54
  55 #define I2C_PMIC        1
  56
  57 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  58
  59 #define DISP0_PWR_EN    IMX_GPIO_NR(1, 21)
  60
  61 #define KEY_VOL_UP      IMX_GPIO_NR(1, 4)
  62
  63 int dram_init(void)
  64 {
  65         gd->ram_size = imx_ddr_size();
  66         return 0;
  67 }
  68
  69 static iomux_v3_cfg_t const uart1_pads[] = {
  70         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  71         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  72 };
  73
  74 static iomux_v3_cfg_t const enet_pads[] = {
  75         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK        | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  86         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  88         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  89         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  90         /* AR8031 PHY Reset */
  91         IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92 };
  93
  94 static void setup_iomux_enet(void)
  95 {
  96         SETUP_IOMUX_PADS(enet_pads);
  97
  98         /* Reset AR8031 PHY */
  99         gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset");
 100         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
 101         mdelay(10);
 102         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
 103         udelay(100);
 104 }
 105
 106 static iomux_v3_cfg_t const usdhc2_pads[] = {
 107         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 108         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 109         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 110         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 111         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 112         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 113         IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 114         IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 115         IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 116         IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 117         IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02     | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 118 };
 119
 120 static iomux_v3_cfg_t const usdhc3_pads[] = {
 121         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 122         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 123         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 124         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 125         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 126         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 127         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 128         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 129         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 130         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 131         IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 132 };
 133
 134 static iomux_v3_cfg_t const usdhc4_pads[] = {
 135         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 136         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 137         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 138         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 139         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 140         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 141         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 142         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 143         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 144         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 145 };
 146
 147 static iomux_v3_cfg_t const ecspi1_pads[] = {
 148         IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 149         IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 150         IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 151         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 152 };
 153
 154 static iomux_v3_cfg_t const rgb_pads[] = {
 155         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
 156         IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 157         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 158         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 159         IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 160         IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 161         IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 162         IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 163         IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 164         IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 165         IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 166         IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 167         IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 168         IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 169         IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 170         IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 171         IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 172         IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 173         IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 174         IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 175         IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 176         IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 177         IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 178         IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 179         IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 180         IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 181         IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 182         IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 183         IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 184 };
 185
 186 static iomux_v3_cfg_t const bl_pads[] = {
 187         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 188 };
 189
 190 static void enable_backlight(void)
 191 {
 192         SETUP_IOMUX_PADS(bl_pads);
 193         gpio_request(DISP0_PWR_EN, "Display Power Enable");
 194         gpio_direction_output(DISP0_PWR_EN, 1);
 195 }
 196
 197 static void enable_rgb(struct display_info_t const *dev)
 198 {
 199         SETUP_IOMUX_PADS(rgb_pads);
 200         enable_backlight();
 201 }
 202
 203 static void enable_lvds(struct display_info_t const *dev)
 204 {
 205         enable_backlight();
 206 }
 207
 208 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
 209         .scl = {
 210                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 211                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 212                 .gp = IMX_GPIO_NR(4, 12)
 213         },
 214         .sda = {
 215                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 216                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 217                 .gp = IMX_GPIO_NR(4, 13)
 218         }
 219 };
 220
 221 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 222         .scl = {
 223                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 224                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 225                 .gp = IMX_GPIO_NR(4, 12)
 226         },
 227         .sda = {
 228                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 229                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 230                 .gp = IMX_GPIO_NR(4, 13)
 231         }
 232 };
 233
 234 static void setup_spi(void)
 235 {
 236         SETUP_IOMUX_PADS(ecspi1_pads);
 237 }
 238
 239 iomux_v3_cfg_t const pcie_pads[] = {
 240         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),        /* POWER */
 241         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),        /* RESET */
 242 };
 243
 244 static void setup_pcie(void)
 245 {
 246         SETUP_IOMUX_PADS(pcie_pads);
 247 }
 248
 249 iomux_v3_cfg_t const di0_pads[] = {
 250         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),        /* DISP0_CLK */
 251         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),               /* DISP0_HSYNC */
 252         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),               /* DISP0_VSYNC */
 253 };
 254
 255 static void setup_iomux_uart(void)
 256 {
 257         SETUP_IOMUX_PADS(uart1_pads);
 258 }
 259
 260 #ifdef CONFIG_FSL_ESDHC
 261 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 262         {USDHC2_BASE_ADDR},
 263         {USDHC3_BASE_ADDR},
 264         {USDHC4_BASE_ADDR},
 265 };
 266
 267 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 268 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 269
 270 int board_mmc_get_env_dev(int devno)
 271 {
 272         return devno - 1;
 273 }
 274
 275 int board_mmc_getcd(struct mmc *mmc)
 276 {
 277         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 278         int ret = 0;
 279
 280         switch (cfg->esdhc_base) {
 281         case USDHC2_BASE_ADDR:
 282                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 283                 break;
 284         case USDHC3_BASE_ADDR:
 285                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 286                 break;
 287         case USDHC4_BASE_ADDR:
 288                 ret = 1; /* eMMC/uSDHC4 is always present */
 289                 break;
 290         }
 291
 292         return ret;
 293 }
 294
 295 int board_mmc_init(bd_t *bis)
 296 {
 297 #ifndef CONFIG_SPL_BUILD
 298         int ret;
 299         int i;
 300
 301         /*
 302          * According to the board_mmc_init() the following map is done:
 303          * (U-Boot device node)    (Physical Port)
 304          * mmc0                    SD2
 305          * mmc1                    SD3
 306          * mmc2                    eMMC
 307          */
 308         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 309                 switch (i) {
 310                 case 0:
 311                         SETUP_IOMUX_PADS(usdhc2_pads);
 312                         gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");
 313                         gpio_direction_input(USDHC2_CD_GPIO);
 314                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 315                         break;
 316                 case 1:
 317                         SETUP_IOMUX_PADS(usdhc3_pads);
 318                         gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");
 319                         gpio_direction_input(USDHC3_CD_GPIO);
 320                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 321                         break;
 322                 case 2:
 323                         SETUP_IOMUX_PADS(usdhc4_pads);
 324                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 325                         break;
 326                 default:
 327                         printf("Warning: you configured more USDHC controllers"
 328                                "(%d) then supported by the board (%d)\n",
 329                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 330                         return -EINVAL;
 331                 }
 332
 333                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 334                 if (ret)
 335                         return ret;
 336         }
 337
 338         return 0;
 339 #else
 340         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 341         unsigned reg = readl(&psrc->sbmr1) >> 11;
 342         /*
 343          * Upon reading BOOT_CFG register the following map is done:
 344          * Bit 11 and 12 of BOOT_CFG register can determine the current
 345          * mmc port
 346          * 0x1                  SD1
 347          * 0x2                  SD2
 348          * 0x3                  SD4
 349          */
 350
 351         switch (reg & 0x3) {
 352         case 0x1:
 353                 SETUP_IOMUX_PADS(usdhc2_pads);
 354                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 355                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 356                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 357                 break;
 358         case 0x2:
 359                 SETUP_IOMUX_PADS(usdhc3_pads);
 360                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 361                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 362                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 363                 break;
 364         case 0x3:
 365                 SETUP_IOMUX_PADS(usdhc4_pads);
 366                 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 367                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 368                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 369                 break;
 370         }
 371
 372         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 373 #endif
 374 }
 375 #endif
 376
 377 static int ar8031_phy_fixup(struct phy_device *phydev)
 378 {
 379         unsigned short val;
 380
 381         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 382         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 383         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 384         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 385
 386         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 387         val &= 0xffe3;
 388         val |= 0x18;
 389         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 390
 391         /* introduce tx clock delay */
 392         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 393         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 394         val |= 0x0100;
 395         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 396
 397         return 0;
 398 }
 399
 400 int board_phy_config(struct phy_device *phydev)
 401 {
 402         ar8031_phy_fixup(phydev);
 403
 404         if (phydev->drv->config)
 405                 phydev->drv->config(phydev);
 406
 407         return 0;
 408 }
 409
 410 #if defined(CONFIG_VIDEO_IPUV3)
 411 static void disable_lvds(struct display_info_t const *dev)
 412 {
 413         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 414
 415         int reg = readl(&iomux->gpr[2]);
 416
 417         reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 418                  IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 419
 420         writel(reg, &iomux->gpr[2]);
 421 }
 422
 423 static void do_enable_hdmi(struct display_info_t const *dev)
 424 {
 425         disable_lvds(dev);
 426         imx_enable_hdmi_phy();
 427 }
 428
 429 struct display_info_t const displays[] = {{
 430         .bus    = -1,
 431         .addr   = 0,
 432         .pixfmt = IPU_PIX_FMT_RGB666,
 433         .detect = NULL,
 434         .enable = enable_lvds,
 435         .mode   = {
 436                 .name           = "Hannstar-XGA",
 437                 .refresh        = 60,
 438                 .xres           = 1024,
 439                 .yres           = 768,
 440                 .pixclock       = 15384,
 441                 .left_margin    = 160,
 442                 .right_margin   = 24,
 443                 .upper_margin   = 29,
 444                 .lower_margin   = 3,
 445                 .hsync_len      = 136,
 446                 .vsync_len      = 6,
 447                 .sync           = FB_SYNC_EXT,
 448                 .vmode          = FB_VMODE_NONINTERLACED
 449 } }, {
 450         .bus    = -1,
 451         .addr   = 0,
 452         .pixfmt = IPU_PIX_FMT_RGB24,
 453         .detect = detect_hdmi,
 454         .enable = do_enable_hdmi,
 455         .mode   = {
 456                 .name           = "HDMI",
 457                 .refresh        = 60,
 458                 .xres           = 1024,
 459                 .yres           = 768,
 460                 .pixclock       = 15384,
 461                 .left_margin    = 160,
 462                 .right_margin   = 24,
 463                 .upper_margin   = 29,
 464                 .lower_margin   = 3,
 465                 .hsync_len      = 136,
 466                 .vsync_len      = 6,
 467                 .sync           = FB_SYNC_EXT,
 468                 .vmode          = FB_VMODE_NONINTERLACED
 469 } }, {
 470         .bus    = 0,
 471         .addr   = 0,
 472         .pixfmt = IPU_PIX_FMT_RGB24,
 473         .detect = NULL,
 474         .enable = enable_rgb,
 475         .mode   = {
 476                 .name           = "SEIKO-WVGA",
 477                 .refresh        = 60,
 478                 .xres           = 800,
 479                 .yres           = 480,
 480                 .pixclock       = 29850,
 481                 .left_margin    = 89,
 482                 .right_margin   = 164,
 483                 .upper_margin   = 23,
 484                 .lower_margin   = 10,
 485                 .hsync_len      = 10,
 486                 .vsync_len      = 10,
 487                 .sync           = 0,
 488                 .vmode          = FB_VMODE_NONINTERLACED
 489 } } };
 490 size_t display_count = ARRAY_SIZE(displays);
 491
 492 static void setup_display(void)
 493 {
 494         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 495         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 496         int reg;
 497
 498         /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
 499         SETUP_IOMUX_PADS(di0_pads);
 500
 501         enable_ipu_clock();
 502         imx_setup_hdmi();
 503
 504         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 505         reg = readl(&mxc_ccm->CCGR3);
 506         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 507         writel(reg, &mxc_ccm->CCGR3);
 508
 509         /* set LDB0, LDB1 clk select to 011/011 */
 510         reg = readl(&mxc_ccm->cs2cdr);
 511         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 512                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 513         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 514               | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 515         writel(reg, &mxc_ccm->cs2cdr);
 516
 517         reg = readl(&mxc_ccm->cscmr2);
 518         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 519         writel(reg, &mxc_ccm->cscmr2);
 520
 521         reg = readl(&mxc_ccm->chsccdr);
 522         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 523                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 524         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 525                 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 526         writel(reg, &mxc_ccm->chsccdr);
 527
 528         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 529              | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 530              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 531              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 532              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 533              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 534              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 535              | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 536              | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 537         writel(reg, &iomux->gpr[2]);
 538
 539         reg = readl(&iomux->gpr[3]);
 540         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
 541                         | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 542             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 543                << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 544         writel(reg, &iomux->gpr[3]);
 545 }
 546 #endif /* CONFIG_VIDEO_IPUV3 */
 547
 548 /*
 549  * Do not overwrite the console
 550  * Use always serial for U-Boot console
 551  */
 552 int overwrite_console(void)
 553 {
 554         return 1;
 555 }
 556
 557 int board_eth_init(bd_t *bis)
 558 {
 559         setup_iomux_enet();
 560         setup_pcie();
 561
 562         return cpu_eth_init(bis);
 563 }
 564
 565 #ifdef CONFIG_USB_EHCI_MX6
 566 static void setup_usb(void)
 567 {
 568         /*
 569          * set daisy chain for otg_pin_id on 6q.
 570          * for 6dl, this bit is reserved
 571          */
 572         imx_iomux_set_gpr_register(1, 13, 1, 0);
 573 }
 574 #endif
 575
 576 int board_early_init_f(void)
 577 {
 578         setup_iomux_uart();
 579
 580         return 0;
 581 }
 582
 583 int board_init(void)
 584 {
 585         /* address of boot parameters */
 586         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 587
 588 #ifdef CONFIG_MXC_SPI
 589         setup_spi();
 590 #endif
 591         if (is_mx6dq() || is_mx6dqp())
 592                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
 593         else
 594                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 595 #if defined(CONFIG_VIDEO_IPUV3)
 596         setup_display();
 597 #endif
 598 #ifdef CONFIG_USB_EHCI_MX6
 599         setup_usb();
 600 #endif
 601
 602         return 0;
 603 }
 604
 605 int power_init_board(void)
 606 {
 607         struct pmic *p;
 608         unsigned int reg;
 609         int ret;
 610
 611         p = pfuze_common_init(I2C_PMIC);
 612         if (!p)
 613                 return -ENODEV;
 614
 615         ret = pfuze_mode_init(p, APS_PFM);
 616         if (ret < 0)
 617                 return ret;
 618
 619         /* Increase VGEN3 from 2.5 to 2.8V */
 620         pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
 621         reg &= ~LDO_VOL_MASK;
 622         reg |= LDOB_2_80V;
 623         pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
 624
 625         /* Increase VGEN5 from 2.8 to 3V */
 626         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 627         reg &= ~LDO_VOL_MASK;
 628         reg |= LDOB_3_00V;
 629         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 630
 631         return 0;
 632 }
 633
 634 #ifdef CONFIG_MXC_SPI
 635 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 636 {
 637         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 638 }
 639 #endif
 640
 641 #ifdef CONFIG_CMD_BMODE
 642 static const struct boot_mode board_boot_modes[] = {
 643         /* 4 bit bus width */
 644         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 645         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 646         /* 8 bit bus width */
 647         {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 648         {NULL,   0},
 649 };
 650 #endif
 651
 652 int board_late_init(void)
 653 {
 654 #ifdef CONFIG_CMD_BMODE
 655         add_board_boot_modes(board_boot_modes);
 656 #endif
 657
 658 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 659         env_set("board_name", "SABRESD");
 660
 661         if (is_mx6dqp())
 662                 env_set("board_rev", "MX6QP");
 663         else if (is_mx6dq())
 664                 env_set("board_rev", "MX6Q");
 665         else if (is_mx6sdl())
 666                 env_set("board_rev", "MX6DL");
 667 #endif
 668
 669         return 0;
 670 }
 671
 672 int checkboard(void)
 673 {
 674         puts("Board: MX6-SabreSD\n");
 675         return 0;
 676 }
 677
 678 #ifdef CONFIG_SPL_BUILD
 679 #include <asm/arch/mx6-ddr.h>
 680 #include <spl.h>
 681 #include <linux/libfdt.h>
 682
 683 #ifdef CONFIG_SPL_OS_BOOT
 684 int spl_start_uboot(void)
 685 {
 686         gpio_request(KEY_VOL_UP, "KEY Volume UP");
 687         gpio_direction_input(KEY_VOL_UP);
 688
 689         /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
 690         return gpio_get_value(KEY_VOL_UP);
 691 }
 692 #endif
 693
 694 static void ccgr_init(void)
 695 {
 696         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 697
 698         writel(0x00C03F3F, &ccm->CCGR0);
 699         writel(0x0030FC03, &ccm->CCGR1);
 700         writel(0x0FFFC000, &ccm->CCGR2);
 701         writel(0x3FF00000, &ccm->CCGR3);
 702         writel(0x00FFF300, &ccm->CCGR4);
 703         writel(0x0F0000C3, &ccm->CCGR5);
 704         writel(0x000003FF, &ccm->CCGR6);
 705 }
 706
 707 static int mx6q_dcd_table[] = {
 708         0x020e0798, 0x000C0000,
 709         0x020e0758, 0x00000000,
 710         0x020e0588, 0x00000030,
 711         0x020e0594, 0x00000030,
 712         0x020e056c, 0x00000030,
 713         0x020e0578, 0x00000030,
 714         0x020e074c, 0x00000030,
 715         0x020e057c, 0x00000030,
 716         0x020e058c, 0x00000000,
 717         0x020e059c, 0x00000030,
 718         0x020e05a0, 0x00000030,
 719         0x020e078c, 0x00000030,
 720         0x020e0750, 0x00020000,
 721         0x020e05a8, 0x00000030,
 722         0x020e05b0, 0x00000030,
 723         0x020e0524, 0x00000030,
 724         0x020e051c, 0x00000030,
 725         0x020e0518, 0x00000030,
 726         0x020e050c, 0x00000030,
 727         0x020e05b8, 0x00000030,
 728         0x020e05c0, 0x00000030,
 729         0x020e0774, 0x00020000,
 730         0x020e0784, 0x00000030,
 731         0x020e0788, 0x00000030,
 732         0x020e0794, 0x00000030,
 733         0x020e079c, 0x00000030,
 734         0x020e07a0, 0x00000030,
 735         0x020e07a4, 0x00000030,
 736         0x020e07a8, 0x00000030,
 737         0x020e0748, 0x00000030,
 738         0x020e05ac, 0x00000030,
 739         0x020e05b4, 0x00000030,
 740         0x020e0528, 0x00000030,
 741         0x020e0520, 0x00000030,
 742         0x020e0514, 0x00000030,
 743         0x020e0510, 0x00000030,
 744         0x020e05bc, 0x00000030,
 745         0x020e05c4, 0x00000030,
 746         0x021b0800, 0xa1390003,
 747         0x021b080c, 0x001F001F,
 748         0x021b0810, 0x001F001F,
 749         0x021b480c, 0x001F001F,
 750         0x021b4810, 0x001F001F,
 751         0x021b083c, 0x43270338,
 752         0x021b0840, 0x03200314,
 753         0x021b483c, 0x431A032F,
 754         0x021b4840, 0x03200263,
 755         0x021b0848, 0x4B434748,
 756         0x021b4848, 0x4445404C,
 757         0x021b0850, 0x38444542,
 758         0x021b4850, 0x4935493A,
 759         0x021b081c, 0x33333333,
 760         0x021b0820, 0x33333333,
 761         0x021b0824, 0x33333333,
 762         0x021b0828, 0x33333333,
 763         0x021b481c, 0x33333333,
 764         0x021b4820, 0x33333333,
 765         0x021b4824, 0x33333333,
 766         0x021b4828, 0x33333333,
 767         0x021b08b8, 0x00000800,
 768         0x021b48b8, 0x00000800,
 769         0x021b0004, 0x00020036,
 770         0x021b0008, 0x09444040,
 771         0x021b000c, 0x555A7975,
 772         0x021b0010, 0xFF538F64,
 773         0x021b0014, 0x01FF00DB,
 774         0x021b0018, 0x00001740,
 775         0x021b001c, 0x00008000,
 776         0x021b002c, 0x000026d2,
 777         0x021b0030, 0x005A1023,
 778         0x021b0040, 0x00000027,
 779         0x021b0000, 0x831A0000,
 780         0x021b001c, 0x04088032,
 781         0x021b001c, 0x00008033,
 782         0x021b001c, 0x00048031,
 783         0x021b001c, 0x09408030,
 784         0x021b001c, 0x04008040,
 785         0x021b0020, 0x00005800,
 786         0x021b0818, 0x00011117,
 787         0x021b4818, 0x00011117,
 788         0x021b0004, 0x00025576,
 789         0x021b0404, 0x00011006,
 790         0x021b001c, 0x00000000,
 791 };
 792
 793 static int mx6qp_dcd_table[] = {
 794         0x020e0798, 0x000c0000,
 795         0x020e0758, 0x00000000,
 796         0x020e0588, 0x00000030,
 797         0x020e0594, 0x00000030,
 798         0x020e056c, 0x00000030,
 799         0x020e0578, 0x00000030,
 800         0x020e074c, 0x00000030,
 801         0x020e057c, 0x00000030,
 802         0x020e058c, 0x00000000,
 803         0x020e059c, 0x00000030,
 804         0x020e05a0, 0x00000030,
 805         0x020e078c, 0x00000030,
 806         0x020e0750, 0x00020000,
 807         0x020e05a8, 0x00000030,
 808         0x020e05b0, 0x00000030,
 809         0x020e0524, 0x00000030,
 810         0x020e051c, 0x00000030,
 811         0x020e0518, 0x00000030,
 812         0x020e050c, 0x00000030,
 813         0x020e05b8, 0x00000030,
 814         0x020e05c0, 0x00000030,
 815         0x020e0774, 0x00020000,
 816         0x020e0784, 0x00000030,
 817         0x020e0788, 0x00000030,
 818         0x020e0794, 0x00000030,
 819         0x020e079c, 0x00000030,
 820         0x020e07a0, 0x00000030,
 821         0x020e07a4, 0x00000030,
 822         0x020e07a8, 0x00000030,
 823         0x020e0748, 0x00000030,
 824         0x020e05ac, 0x00000030,
 825         0x020e05b4, 0x00000030,
 826         0x020e0528, 0x00000030,
 827         0x020e0520, 0x00000030,
 828         0x020e0514, 0x00000030,
 829         0x020e0510, 0x00000030,
 830         0x020e05bc, 0x00000030,
 831         0x020e05c4, 0x00000030,
 832         0x021b0800, 0xa1390003,
 833         0x021b080c, 0x001b001e,
 834         0x021b0810, 0x002e0029,
 835         0x021b480c, 0x001b002a,
 836         0x021b4810, 0x0019002c,
 837         0x021b083c, 0x43240334,
 838         0x021b0840, 0x0324031a,
 839         0x021b483c, 0x43340344,
 840         0x021b4840, 0x03280276,
 841         0x021b0848, 0x44383A3E,
 842         0x021b4848, 0x3C3C3846,
 843         0x021b0850, 0x2e303230,
 844         0x021b4850, 0x38283E34,
 845         0x021b081c, 0x33333333,
 846         0x021b0820, 0x33333333,
 847         0x021b0824, 0x33333333,
 848         0x021b0828, 0x33333333,
 849         0x021b481c, 0x33333333,
 850         0x021b4820, 0x33333333,
 851         0x021b4824, 0x33333333,
 852         0x021b4828, 0x33333333,
 853         0x021b08c0, 0x24912249,
 854         0x021b48c0, 0x24914289,
 855         0x021b08b8, 0x00000800,
 856         0x021b48b8, 0x00000800,
 857         0x021b0004, 0x00020036,
 858         0x021b0008, 0x24444040,
 859         0x021b000c, 0x555A7955,
 860         0x021b0010, 0xFF320F64,
 861         0x021b0014, 0x01ff00db,
 862         0x021b0018, 0x00001740,
 863         0x021b001c, 0x00008000,
 864         0x021b002c, 0x000026d2,
 865         0x021b0030, 0x005A1023,
 866         0x021b0040, 0x00000027,
 867         0x021b0400, 0x14420000,
 868         0x021b0000, 0x831A0000,
 869         0x021b0890, 0x00400C58,
 870         0x00bb0008, 0x00000000,
 871         0x00bb000c, 0x2891E41A,
 872         0x00bb0038, 0x00000564,
 873         0x00bb0014, 0x00000040,
 874         0x00bb0028, 0x00000020,
 875         0x00bb002c, 0x00000020,
 876         0x021b001c, 0x04088032,
 877         0x021b001c, 0x00008033,
 878         0x021b001c, 0x00048031,
 879         0x021b001c, 0x09408030,
 880         0x021b001c, 0x04008040,
 881         0x021b0020, 0x00005800,
 882         0x021b0818, 0x00011117,
 883         0x021b4818, 0x00011117,
 884         0x021b0004, 0x00025576,
 885         0x021b0404, 0x00011006,
 886         0x021b001c, 0x00000000,
 887 };
 888
 889 static int mx6dl_dcd_table[] = {
 890         0x020e0774, 0x000C0000,
 891         0x020e0754, 0x00000000,
 892         0x020e04ac, 0x00000030,
 893         0x020e04b0, 0x00000030,
 894         0x020e0464, 0x00000030,
 895         0x020e0490, 0x00000030,
 896         0x020e074c, 0x00000030,
 897         0x020e0494, 0x00000030,
 898         0x020e04a0, 0x00000000,
 899         0x020e04b4, 0x00000030,
 900         0x020e04b8, 0x00000030,
 901         0x020e076c, 0x00000030,
 902         0x020e0750, 0x00020000,
 903         0x020e04bc, 0x00000030,
 904         0x020e04c0, 0x00000030,
 905         0x020e04c4, 0x00000030,
 906         0x020e04c8, 0x00000030,
 907         0x020e04cc, 0x00000030,
 908         0x020e04d0, 0x00000030,
 909         0x020e04d4, 0x00000030,
 910         0x020e04d8, 0x00000030,
 911         0x020e0760, 0x00020000,
 912         0x020e0764, 0x00000030,
 913         0x020e0770, 0x00000030,
 914         0x020e0778, 0x00000030,
 915         0x020e077c, 0x00000030,
 916         0x020e0780, 0x00000030,
 917         0x020e0784, 0x00000030,
 918         0x020e078c, 0x00000030,
 919         0x020e0748, 0x00000030,
 920         0x020e0470, 0x00000030,
 921         0x020e0474, 0x00000030,
 922         0x020e0478, 0x00000030,
 923         0x020e047c, 0x00000030,
 924         0x020e0480, 0x00000030,
 925         0x020e0484, 0x00000030,
 926         0x020e0488, 0x00000030,
 927         0x020e048c, 0x00000030,
 928         0x021b0800, 0xa1390003,
 929         0x021b080c, 0x001F001F,
 930         0x021b0810, 0x001F001F,
 931         0x021b480c, 0x001F001F,
 932         0x021b4810, 0x001F001F,
 933         0x021b083c, 0x4220021F,
 934         0x021b0840, 0x0207017E,
 935         0x021b483c, 0x4201020C,
 936         0x021b4840, 0x01660172,
 937         0x021b0848, 0x4A4D4E4D,
 938         0x021b4848, 0x4A4F5049,
 939         0x021b0850, 0x3F3C3D31,
 940         0x021b4850, 0x3238372B,
 941         0x021b081c, 0x33333333,
 942         0x021b0820, 0x33333333,
 943         0x021b0824, 0x33333333,
 944         0x021b0828, 0x33333333,
 945         0x021b481c, 0x33333333,
 946         0x021b4820, 0x33333333,
 947         0x021b4824, 0x33333333,
 948         0x021b4828, 0x33333333,
 949         0x021b08b8, 0x00000800,
 950         0x021b48b8, 0x00000800,
 951         0x021b0004, 0x0002002D,
 952         0x021b0008, 0x00333030,
 953         0x021b000c, 0x3F435313,
 954         0x021b0010, 0xB66E8B63,
 955         0x021b0014, 0x01FF00DB,
 956         0x021b0018, 0x00001740,
 957         0x021b001c, 0x00008000,
 958         0x021b002c, 0x000026d2,
 959         0x021b0030, 0x00431023,
 960         0x021b0040, 0x00000027,
 961         0x021b0000, 0x831A0000,
 962         0x021b001c, 0x04008032,
 963         0x021b001c, 0x00008033,
 964         0x021b001c, 0x00048031,
 965         0x021b001c, 0x05208030,
 966         0x021b001c, 0x04008040,
 967         0x021b0020, 0x00005800,
 968         0x021b0818, 0x00011117,
 969         0x021b4818, 0x00011117,
 970         0x021b0004, 0x0002556D,
 971         0x021b0404, 0x00011006,
 972         0x021b001c, 0x00000000,
 973 };
 974
 975 static void ddr_init(int *table, int size)
 976 {
 977         int i;
 978
 979         for (i = 0; i < size / 2 ; i++)
 980                 writel(table[2 * i + 1], table[2 * i]);
 981 }
 982
 983 static void spl_dram_init(void)
 984 {
 985         if (is_mx6dq())
 986                 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
 987         else if (is_mx6dqp())
 988                 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
 989         else if (is_mx6sdl())
 990                 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
 991 }
 992
 993 void board_init_f(ulong dummy)
 994 {
 995         /* DDR initialization */
 996         spl_dram_init();
 997
 998         /* setup AIPS and disable watchdog */
 999         arch_cpu_init();
1000
1001         ccgr_init();
1002         gpr_init();
1003
1004         /* iomux and setup of i2c */
1005         board_early_init_f();
1006
1007         /* setup GP timer */
1008         timer_init();
1009
1010         /* UART clocks enabled and gd valid - init serial console */
1011         preloader_console_init();
1012
1013         /* Clear the BSS. */
1014         memset(__bss_start, 0, __bss_end - __bss_start);
1015
1016         /* load/boot image from boot device */
1017         board_init_r(NULL, 0);
1018 }
1019 #endif
1020
1021 #ifdef CONFIG_SPL_LOAD_FIT
1022 int board_fit_config_name_match(const char *name)
1023 {
1024         if (is_mx6dq()) {
1025                 if (!strcmp(name, "imx6q-sabresd"))
1026                         return 0;
1027         } else if (is_mx6dqp()) {
1028                 if (!strcmp(name, "imx6qp-sabresd"))
1029                         return 0;
1030         } else if (is_mx6dl()) {
1031                 if (!strcmp(name, "imx6dl-sabresd"))
1032                         return 0;
1033         }
1034
1035         return -1;
1036 }
1037 #endif