board/freescale/mx53loco/mx53loco.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   4  * Jason Liu <r64343@freescale.com>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <asm/global_data.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/iomux-mx53.h>
  17 #include <asm/arch/clock.h>
  18 #include <env.h>
  19 #include <linux/errno.h>
  20 #include <asm/mach-imx/mx5_video.h>
  21 #include <netdev.h>
  22 #include <i2c.h>
  23 #include <input.h>
  24 #include <mmc.h>
  25 #include <fsl_esdhc_imx.h>
  26 #include <asm/gpio.h>
  27 #include <power/pmic.h>
  28 #include <dialog_pmic.h>
  29 #include <fsl_pmic.h>
  30 #include <linux/fb.h>
  31 #include <ipu_pixfmt.h>
  32
  33 #define MX53LOCO_LCD_POWER              IMX_GPIO_NR(3, 24)
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 u32 get_board_rev(void)
  38 {
  39         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  40         struct fuse_bank *bank = &iim->bank[0];
  41         struct fuse_bank0_regs *fuse =
  42                 (struct fuse_bank0_regs *)bank->fuse_regs;
  43
  44         int rev = readl(&fuse->gp[6]);
  45
  46         if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
  47                 rev = 0;
  48
  49         return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  50 }
  51
  52 #define UART_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  53                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  54
  55 static void setup_iomux_uart(void)
  56 {
  57         static const iomux_v3_cfg_t uart_pads[] = {
  58                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
  59                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
  60         };
  61
  62         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  63 }
  64
  65 #ifdef CONFIG_USB_EHCI_MX5
  66 int board_ehci_hcd_init(int port)
  67 {
  68         /* request VBUS power enable pin, GPIO7_8 */
  69         imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
  70         gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
  71         return 0;
  72 }
  73 #endif
  74
  75 static void setup_iomux_fec(void)
  76 {
  77         static const iomux_v3_cfg_t fec_pads[] = {
  78                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  79                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  80                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  81                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  82                                 PAD_CTL_HYS | PAD_CTL_PKE),
  83                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  84                                 PAD_CTL_HYS | PAD_CTL_PKE),
  85                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
  86                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
  87                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  88                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  89                                 PAD_CTL_HYS | PAD_CTL_PKE),
  90                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  91                                 PAD_CTL_HYS | PAD_CTL_PKE),
  92                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  93                                 PAD_CTL_HYS | PAD_CTL_PKE),
  94         };
  95
  96         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  97 }
  98
  99 #ifdef CONFIG_FSL_ESDHC_IMX
 100 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 101         {MMC_SDHC1_BASE_ADDR},
 102         {MMC_SDHC3_BASE_ADDR},
 103 };
 104
 105 int board_mmc_getcd(struct mmc *mmc)
 106 {
 107         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 108         int ret;
 109
 110         imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
 111         gpio_direction_input(IMX_GPIO_NR(3, 11));
 112         imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
 113         gpio_direction_input(IMX_GPIO_NR(3, 13));
 114
 115         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 116                 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
 117         else
 118                 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
 119
 120         return ret;
 121 }
 122
 123 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 124                                  PAD_CTL_PUS_100K_UP)
 125 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 126                                  PAD_CTL_DSE_HIGH)
 127
 128 int board_mmc_init(struct bd_info *bis)
 129 {
 130         static const iomux_v3_cfg_t sd1_pads[] = {
 131                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 132                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 133                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 134                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 135                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 136                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 137                 MX53_PAD_EIM_DA13__GPIO3_13,
 138         };
 139
 140         static const iomux_v3_cfg_t sd2_pads[] = {
 141                 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
 142                                 SD_CMD_PAD_CTRL),
 143                 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
 144                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
 145                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
 146                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
 147                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
 148                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
 149                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
 150                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
 151                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
 152                 MX53_PAD_EIM_DA11__GPIO3_11,
 153         };
 154
 155         u32 index;
 156         int ret;
 157
 158         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 159         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 160
 161         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 162                 switch (index) {
 163                 case 0:
 164                         imx_iomux_v3_setup_multiple_pads(sd1_pads,
 165                                                          ARRAY_SIZE(sd1_pads));
 166                         break;
 167                 case 1:
 168                         imx_iomux_v3_setup_multiple_pads(sd2_pads,
 169                                                          ARRAY_SIZE(sd2_pads));
 170                         break;
 171                 default:
 172                         printf("Warning: you configured more ESDHC controller"
 173                                 "(%d) as supported by the board(2)\n",
 174                                 CONFIG_SYS_FSL_ESDHC_NUM);
 175                         return -EINVAL;
 176                 }
 177                 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 178                 if (ret)
 179                         return ret;
 180         }
 181
 182         return 0;
 183 }
 184 #endif
 185
 186 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 187                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 188
 189 static void setup_iomux_i2c(void)
 190 {
 191         static const iomux_v3_cfg_t i2c1_pads[] = {
 192                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
 193                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
 194         };
 195
 196         imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
 197 }
 198
 199 static int power_init(void)
 200 {
 201         unsigned int val;
 202         int ret;
 203         struct pmic *p;
 204
 205         if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
 206                 ret = pmic_dialog_init(I2C_PMIC);
 207                 if (ret)
 208                         return ret;
 209
 210                 p = pmic_get("DIALOG_PMIC");
 211                 if (!p)
 212                         return -ENODEV;
 213
 214                 env_set("fdt_file", "imx53-qsb.dtb");
 215
 216                 /* Set VDDA to 1.25V */
 217                 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
 218                 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
 219                 if (ret) {
 220                         printf("Writing to BUCKCORE_REG failed: %d\n", ret);
 221                         return ret;
 222                 }
 223
 224                 pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
 225                 val |= DA9052_SUPPLY_VBCOREGO;
 226                 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
 227                 if (ret) {
 228                         printf("Writing to SUPPLY_REG failed: %d\n", ret);
 229                         return ret;
 230                 }
 231
 232                 /* Set Vcc peripheral to 1.30V */
 233                 ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
 234                 if (ret) {
 235                         printf("Writing to BUCKPRO_REG failed: %d\n", ret);
 236                         return ret;
 237                 }
 238
 239                 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
 240                 if (ret) {
 241                         printf("Writing to SUPPLY_REG failed: %d\n", ret);
 242                         return ret;
 243                 }
 244
 245                 return ret;
 246         }
 247
 248         if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
 249                 ret = pmic_init(I2C_0);
 250                 if (ret)
 251                         return ret;
 252
 253                 p = pmic_get("FSL_PMIC");
 254                 if (!p)
 255                         return -ENODEV;
 256
 257                 env_set("fdt_file", "imx53-qsrb.dtb");
 258
 259                 /* Set VDDGP to 1.25V for 1GHz on SW1 */
 260                 pmic_reg_read(p, REG_SW_0, &val);
 261                 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
 262                 ret = pmic_reg_write(p, REG_SW_0, val);
 263                 if (ret) {
 264                         printf("Writing to REG_SW_0 failed: %d\n", ret);
 265                         return ret;
 266                 }
 267
 268                 /* Set VCC as 1.30V on SW2 */
 269                 pmic_reg_read(p, REG_SW_1, &val);
 270                 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
 271                 ret = pmic_reg_write(p, REG_SW_1, val);
 272                 if (ret) {
 273                         printf("Writing to REG_SW_1 failed: %d\n", ret);
 274                         return ret;
 275                 }
 276
 277                 /* Set global reset timer to 4s */
 278                 pmic_reg_read(p, REG_POWER_CTL2, &val);
 279                 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
 280                 ret = pmic_reg_write(p, REG_POWER_CTL2, val);
 281                 if (ret) {
 282                         printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
 283                         return ret;
 284                 }
 285
 286                 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
 287                 pmic_reg_read(p, REG_MODE_0, &val);
 288                 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
 289                 ret = pmic_reg_write(p, REG_MODE_0, val);
 290                 if (ret) {
 291                         printf("Writing to REG_MODE_0 failed: %d\n", ret);
 292                         return ret;
 293                 }
 294
 295                 /* Set SWBST to 5V in auto mode */
 296                 val = SWBST_AUTO;
 297                 ret = pmic_reg_write(p, SWBST_CTRL, val);
 298                 if (ret) {
 299                         printf("Writing to SWBST_CTRL failed: %d\n", ret);
 300                         return ret;
 301                 }
 302
 303                 return ret;
 304         }
 305
 306         return -1;
 307 }
 308
 309 static void clock_1GHz(void)
 310 {
 311         int ret;
 312         u32 ref_clk = MXC_HCLK;
 313         /*
 314          * After increasing voltage to 1.25V, we can switch
 315          * CPU clock to 1GHz and DDR to 400MHz safely
 316          */
 317         ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
 318         if (ret)
 319                 printf("CPU:   Switch CPU clock to 1GHZ failed\n");
 320
 321         ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
 322         ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
 323         if (ret)
 324                 printf("CPU:   Switch DDR clock to 400MHz failed\n");
 325 }
 326
 327 int board_early_init_f(void)
 328 {
 329         setup_iomux_uart();
 330         setup_iomux_fec();
 331         setup_iomux_lcd();
 332
 333         return 0;
 334 }
 335
 336 /*
 337  * Do not overwrite the console
 338  * Use always serial for U-Boot console
 339  */
 340 int overwrite_console(void)
 341 {
 342         return 1;
 343 }
 344
 345 int board_init(void)
 346 {
 347         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 348
 349         mxc_set_sata_internal_clock();
 350         setup_iomux_i2c();
 351
 352         return 0;
 353 }
 354
 355 int board_late_init(void)
 356 {
 357         if (!power_init())
 358                 clock_1GHz();
 359
 360         return 0;
 361 }
 362
 363 int checkboard(void)
 364 {
 365         puts("Board: MX53 LOCO\n");
 366
 367         return 0;
 368 }