2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/iomux.h>
31 #include <asm/arch/clock.h>
32 #include <asm/errno.h>
36 #include <fsl_esdhc.h>
39 DECLARE_GLOBAL_DATA_PTR;
45 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
46 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
48 gd->ram_size = size1 + size2;
52 void dram_init_banksize(void)
54 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
55 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
57 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
58 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
61 static void setup_iomux_uart(void)
64 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
65 mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
66 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
67 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
68 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
69 PAD_CTL_ODE_OPENDRAIN_ENABLE);
70 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
73 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
74 mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
75 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
76 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
77 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
78 PAD_CTL_ODE_OPENDRAIN_ENABLE);
81 static void setup_iomux_fec(void)
84 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
85 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
86 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
87 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
88 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
89 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
92 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
93 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
96 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
97 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
98 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
101 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
102 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
103 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
106 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
107 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
110 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
111 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
114 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
115 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
118 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
119 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
120 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
123 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
124 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
125 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
128 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
129 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
130 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
133 #ifdef CONFIG_FSL_ESDHC
134 struct fsl_esdhc_cfg esdhc_cfg[2] = {
135 {MMC_SDHC1_BASE_ADDR, 1},
136 {MMC_SDHC3_BASE_ADDR, 1},
139 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
141 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
143 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
144 *cd = gpio_get_value(77); /*GPIO3_13*/
146 *cd = gpio_get_value(75); /*GPIO3_11*/
151 int board_mmc_init(bd_t *bis)
156 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
159 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
160 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
161 mxc_request_iomux(MX53_PIN_SD1_DATA0,
163 mxc_request_iomux(MX53_PIN_SD1_DATA1,
165 mxc_request_iomux(MX53_PIN_SD1_DATA2,
167 mxc_request_iomux(MX53_PIN_SD1_DATA3,
169 mxc_request_iomux(MX53_PIN_EIM_DA13,
172 mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
173 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
174 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
175 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
176 mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
177 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
178 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
180 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
181 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
182 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
183 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
184 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
185 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
186 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
187 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
188 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
189 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
190 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
191 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
192 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
193 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
194 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
195 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
198 mxc_request_iomux(MX53_PIN_ATA_RESET_B,
200 mxc_request_iomux(MX53_PIN_ATA_IORDY,
202 mxc_request_iomux(MX53_PIN_ATA_DATA8,
204 mxc_request_iomux(MX53_PIN_ATA_DATA9,
206 mxc_request_iomux(MX53_PIN_ATA_DATA10,
208 mxc_request_iomux(MX53_PIN_ATA_DATA11,
210 mxc_request_iomux(MX53_PIN_ATA_DATA0,
212 mxc_request_iomux(MX53_PIN_ATA_DATA1,
214 mxc_request_iomux(MX53_PIN_ATA_DATA2,
216 mxc_request_iomux(MX53_PIN_ATA_DATA3,
218 mxc_request_iomux(MX53_PIN_EIM_DA11,
221 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
222 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
223 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
224 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
225 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
226 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
227 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
229 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
230 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
231 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
232 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
233 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
234 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
235 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
236 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
237 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
238 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
239 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
240 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
241 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
242 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
243 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
244 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
245 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
246 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
247 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
248 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
249 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
250 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
251 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
252 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
253 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
254 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
255 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
256 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
257 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
258 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
259 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
260 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
264 printf("Warning: you configured more ESDHC controller"
265 "(%d) as supported by the board(2)\n",
266 CONFIG_SYS_FSL_ESDHC_NUM);
269 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
276 int board_early_init_f(void)
286 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
293 puts("Board: MX53 LOCO\n");