2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/iomux.h>
32 #include <asm/arch/clock.h>
33 #include <asm/errno.h>
37 #include <fsl_esdhc.h>
40 #include <dialog_pmic.h>
43 DECLARE_GLOBAL_DATA_PTR;
49 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
50 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
52 gd->ram_size = size1 + size2;
56 void dram_init_banksize(void)
58 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
59 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
61 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
62 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
65 static void setup_iomux_uart(void)
68 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
69 mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
70 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
71 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
72 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
73 PAD_CTL_ODE_OPENDRAIN_ENABLE);
74 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
77 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
78 mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
79 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
80 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
81 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
82 PAD_CTL_ODE_OPENDRAIN_ENABLE);
85 #ifdef CONFIG_USB_EHCI_MX5
86 int board_ehci_hcd_init(int port)
88 /* request VBUS power enable pin, GPIO[8}, gpio7 */
89 mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
90 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
91 gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
96 static void setup_iomux_fec(void)
99 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
100 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
101 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
102 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
103 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
104 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
107 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
108 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
111 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
112 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
113 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
116 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
117 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
118 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
121 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
122 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
125 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
126 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
129 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
130 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
133 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
134 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
135 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
138 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
139 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
140 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
143 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
144 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
145 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
148 #ifdef CONFIG_FSL_ESDHC
149 struct fsl_esdhc_cfg esdhc_cfg[2] = {
150 {MMC_SDHC1_BASE_ADDR, 1},
151 {MMC_SDHC3_BASE_ADDR, 1},
154 int board_mmc_getcd(struct mmc *mmc)
156 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
159 mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
160 gpio_direction_input(75);
161 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
162 gpio_direction_input(77);
164 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
165 ret = !gpio_get_value(77); /* GPIO3_13 */
167 ret = !gpio_get_value(75); /* GPIO3_11 */
172 int board_mmc_init(bd_t *bis)
177 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
180 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
181 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
182 mxc_request_iomux(MX53_PIN_SD1_DATA0,
184 mxc_request_iomux(MX53_PIN_SD1_DATA1,
186 mxc_request_iomux(MX53_PIN_SD1_DATA2,
188 mxc_request_iomux(MX53_PIN_SD1_DATA3,
190 mxc_request_iomux(MX53_PIN_EIM_DA13,
193 mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
194 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
195 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
196 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
197 mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
198 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
199 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
201 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
202 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
203 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
204 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
205 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
206 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
207 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
208 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
209 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
210 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
211 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
212 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
213 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
214 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
215 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
216 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
219 mxc_request_iomux(MX53_PIN_ATA_RESET_B,
221 mxc_request_iomux(MX53_PIN_ATA_IORDY,
223 mxc_request_iomux(MX53_PIN_ATA_DATA8,
225 mxc_request_iomux(MX53_PIN_ATA_DATA9,
227 mxc_request_iomux(MX53_PIN_ATA_DATA10,
229 mxc_request_iomux(MX53_PIN_ATA_DATA11,
231 mxc_request_iomux(MX53_PIN_ATA_DATA0,
233 mxc_request_iomux(MX53_PIN_ATA_DATA1,
235 mxc_request_iomux(MX53_PIN_ATA_DATA2,
237 mxc_request_iomux(MX53_PIN_ATA_DATA3,
239 mxc_request_iomux(MX53_PIN_EIM_DA11,
242 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
243 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
244 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
245 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
246 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
247 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
248 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
250 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
251 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
252 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
253 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
254 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
255 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
256 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
257 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
258 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
259 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
260 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
261 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
262 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
263 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
264 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
265 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
266 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
267 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
268 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
269 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
270 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
271 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
272 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
273 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
274 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
275 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
276 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
277 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
278 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
279 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
280 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
281 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
285 printf("Warning: you configured more ESDHC controller"
286 "(%d) as supported by the board(2)\n",
287 CONFIG_SYS_FSL_ESDHC_NUM);
290 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
297 static void setup_iomux_i2c(void)
300 mxc_request_iomux(MX53_PIN_CSI0_D8,
301 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
302 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
304 mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
305 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
306 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
308 PAD_CTL_ODE_OPENDRAIN_ENABLE);
310 mxc_request_iomux(MX53_PIN_CSI0_D9,
311 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
312 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
314 mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
315 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
316 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
318 PAD_CTL_ODE_OPENDRAIN_ENABLE);
321 static int power_init(void)
327 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
331 /* Set VDDA to 1.25V */
332 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
333 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
335 ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
336 val |= DA9052_SUPPLY_VBCOREGO;
337 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
339 /* Set Vcc peripheral to 1.30V */
340 ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
341 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
344 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
348 /* Set VDDGP to 1.25V for 1GHz on SW1 */
349 pmic_reg_read(p, REG_SW_0, &val);
350 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
351 ret = pmic_reg_write(p, REG_SW_0, val);
353 /* Set VCC as 1.30V on SW2 */
354 pmic_reg_read(p, REG_SW_1, &val);
355 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
356 ret |= pmic_reg_write(p, REG_SW_1, val);
358 /* Set global reset timer to 4s */
359 pmic_reg_read(p, REG_POWER_CTL2, &val);
360 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
361 ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
363 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
364 pmic_reg_read(p, REG_MODE_0, &val);
365 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
366 ret |= pmic_reg_write(p, REG_MODE_0, val);
368 /* Set SWBST to 5V in auto mode */
370 ret |= pmic_reg_write(p, SWBST_CTRL, val);
376 static void clock_1GHz(void)
379 u32 ref_clk = CONFIG_SYS_MX5_HCLK;
381 * After increasing voltage to 1.25V, we can switch
382 * CPU clock to 1GHz and DDR to 400MHz safely
384 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
386 printf("CPU: Switch CPU clock to 1GHZ failed\n");
388 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
389 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
391 printf("CPU: Switch DDR clock to 400MHz failed\n");
394 int board_early_init_f(void)
402 int print_cpuinfo(void)
406 cpurev = get_cpu_rev();
407 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
408 (cpurev & 0xFF000) >> 12,
409 (cpurev & 0x000F0) >> 4,
410 (cpurev & 0x0000F) >> 0,
411 mxc_get_clock(MXC_ARM_CLK) / 1000000);
412 printf("Reset cause: %s\n", get_reset_cause());
416 #ifdef CONFIG_BOARD_LATE_INIT
417 int board_late_init(void)
430 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
432 mxc_set_sata_internal_clock();
439 puts("Board: MX53 LOCO\n");