2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/iomux.h>
32 #include <asm/arch/clock.h>
33 #include <asm/errno.h>
37 #include <fsl_esdhc.h>
40 #include <dialog_pmic.h>
43 #include <ipu_pixfmt.h>
45 #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
47 DECLARE_GLOBAL_DATA_PTR;
53 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
54 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
56 gd->ram_size = size1 + size2;
60 void dram_init_banksize(void)
62 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
63 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
65 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
66 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
69 u32 get_board_rev(void)
71 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
72 struct fuse_bank *bank = &iim->bank[0];
73 struct fuse_bank0_regs *fuse =
74 (struct fuse_bank0_regs *)bank->fuse_regs;
76 int rev = readl(&fuse->gp[6]);
78 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
81 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
84 static void setup_iomux_uart(void)
87 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
88 mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
89 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
90 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
91 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
92 PAD_CTL_ODE_OPENDRAIN_ENABLE);
93 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
96 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
97 mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
98 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
99 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
100 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
101 PAD_CTL_ODE_OPENDRAIN_ENABLE);
104 #ifdef CONFIG_USB_EHCI_MX5
105 int board_ehci_hcd_init(int port)
107 /* request VBUS power enable pin, GPIO7_8 */
108 mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
109 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
114 static void setup_iomux_fec(void)
117 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
118 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
119 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
120 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
121 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
122 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
125 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
126 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
129 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
130 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
131 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
134 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
135 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
136 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
139 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
140 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
143 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
144 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
147 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
148 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
151 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
152 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
153 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
156 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
157 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
158 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
161 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
162 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
163 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
166 #ifdef CONFIG_FSL_ESDHC
167 struct fsl_esdhc_cfg esdhc_cfg[2] = {
168 {MMC_SDHC1_BASE_ADDR},
169 {MMC_SDHC3_BASE_ADDR},
172 int board_mmc_getcd(struct mmc *mmc)
174 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
177 mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
178 gpio_direction_input(IMX_GPIO_NR(3, 11));
179 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
180 gpio_direction_input(IMX_GPIO_NR(3, 13));
182 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
183 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
185 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
190 int board_mmc_init(bd_t *bis)
195 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
196 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
198 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
201 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
202 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
203 mxc_request_iomux(MX53_PIN_SD1_DATA0,
205 mxc_request_iomux(MX53_PIN_SD1_DATA1,
207 mxc_request_iomux(MX53_PIN_SD1_DATA2,
209 mxc_request_iomux(MX53_PIN_SD1_DATA3,
211 mxc_request_iomux(MX53_PIN_EIM_DA13,
214 mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
215 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
216 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
217 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
218 mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
219 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
220 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
222 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
223 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
224 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
225 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
226 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
227 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
228 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
229 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
230 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
231 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
232 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
233 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
234 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
235 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
236 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
237 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
240 mxc_request_iomux(MX53_PIN_ATA_RESET_B,
242 mxc_request_iomux(MX53_PIN_ATA_IORDY,
244 mxc_request_iomux(MX53_PIN_ATA_DATA8,
246 mxc_request_iomux(MX53_PIN_ATA_DATA9,
248 mxc_request_iomux(MX53_PIN_ATA_DATA10,
250 mxc_request_iomux(MX53_PIN_ATA_DATA11,
252 mxc_request_iomux(MX53_PIN_ATA_DATA0,
254 mxc_request_iomux(MX53_PIN_ATA_DATA1,
256 mxc_request_iomux(MX53_PIN_ATA_DATA2,
258 mxc_request_iomux(MX53_PIN_ATA_DATA3,
260 mxc_request_iomux(MX53_PIN_EIM_DA11,
263 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
264 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
265 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
266 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
267 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
268 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
269 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
271 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
272 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
273 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
274 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
275 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
276 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
277 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
278 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
279 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
280 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
281 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
282 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
283 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
284 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
285 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
286 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
287 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
288 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
289 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
290 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
291 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
292 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
293 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
294 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
295 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
296 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
297 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
298 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
299 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
300 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
301 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
302 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
306 printf("Warning: you configured more ESDHC controller"
307 "(%d) as supported by the board(2)\n",
308 CONFIG_SYS_FSL_ESDHC_NUM);
311 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
318 static void setup_iomux_i2c(void)
321 mxc_request_iomux(MX53_PIN_CSI0_D8,
322 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
323 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
325 mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
326 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
327 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
329 PAD_CTL_ODE_OPENDRAIN_ENABLE);
331 mxc_request_iomux(MX53_PIN_CSI0_D9,
332 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
333 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
335 mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
336 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
337 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
339 PAD_CTL_ODE_OPENDRAIN_ENABLE);
342 static int power_init(void)
348 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
352 /* Set VDDA to 1.25V */
353 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
354 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
356 ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
357 val |= DA9052_SUPPLY_VBCOREGO;
358 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
360 /* Set Vcc peripheral to 1.30V */
361 ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
362 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
365 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
369 /* Set VDDGP to 1.25V for 1GHz on SW1 */
370 pmic_reg_read(p, REG_SW_0, &val);
371 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
372 ret = pmic_reg_write(p, REG_SW_0, val);
374 /* Set VCC as 1.30V on SW2 */
375 pmic_reg_read(p, REG_SW_1, &val);
376 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
377 ret |= pmic_reg_write(p, REG_SW_1, val);
379 /* Set global reset timer to 4s */
380 pmic_reg_read(p, REG_POWER_CTL2, &val);
381 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
382 ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
384 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
385 pmic_reg_read(p, REG_MODE_0, &val);
386 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
387 ret |= pmic_reg_write(p, REG_MODE_0, val);
389 /* Set SWBST to 5V in auto mode */
391 ret |= pmic_reg_write(p, SWBST_CTRL, val);
397 static void clock_1GHz(void)
400 u32 ref_clk = MXC_HCLK;
402 * After increasing voltage to 1.25V, we can switch
403 * CPU clock to 1GHz and DDR to 400MHz safely
405 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
407 printf("CPU: Switch CPU clock to 1GHZ failed\n");
409 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
410 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
412 printf("CPU: Switch DDR clock to 400MHz failed\n");
415 static struct fb_videomode const claa_wvga = {
416 .name = "CLAA07LC0ACW",
428 .vmode = FB_VMODE_NONINTERLACED
433 mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0);
434 mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0);
435 mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0);
436 mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0);
437 mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0);
438 mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0);
439 mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0);
440 mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0);
441 mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0);
442 mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0);
443 mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0);
444 mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0);
445 mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0);
446 mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0);
447 mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0);
448 mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0);
449 mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0);
450 mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0);
451 mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0);
452 mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0);
453 mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0);
454 mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0);
455 mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0);
456 mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0);
457 mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0);
458 mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0);
459 mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0);
460 mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0);
462 /* Turn on GPIO backlight */
463 mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1);
464 gpio_direction_output(MX53LOCO_LCD_POWER, 1);
466 /* Turn on display contrast */
467 mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
468 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1);
471 void lcd_enable(void)
473 int ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
475 printf("LCD cannot be configured: %d\n", ret);
478 int board_early_init_f(void)
487 int print_cpuinfo(void)
491 cpurev = get_cpu_rev();
492 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
493 (cpurev & 0xFF000) >> 12,
494 (cpurev & 0x000F0) >> 4,
495 (cpurev & 0x0000F) >> 0,
496 mxc_get_clock(MXC_ARM_CLK) / 1000000);
497 printf("Reset cause: %s\n", get_reset_cause());
502 * Do not overwrite the console
503 * Use always serial for U-Boot console
505 int overwrite_console(void)
512 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
514 mxc_set_sata_internal_clock();
527 puts("Board: MX53 LOCO\n");