board/freescale/mx53evk/mx53evk.c

   1 /*
   2  * (C) Copyright 2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/errno.h>
  31 #include <netdev.h>
  32 #include <i2c.h>
  33 #include <mmc.h>
  34 #include <fsl_esdhc.h>
  35 #include <pmic.h>
  36 #include <fsl_pmic.h>
  37 #include <asm/gpio.h>
  38 #include <mc13892.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 int dram_init(void)
  43 {
  44         /* dram_init must store complete ramsize in gd->ram_size */
  45         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  46                                 PHYS_SDRAM_1_SIZE);
  47         return 0;
  48 }
  49
  50 static void setup_iomux_uart(void)
  51 {
  52         /* UART1 RXD */
  53         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
  54         mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
  55                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  56                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  57                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  58                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  59         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
  60
  61         /* UART1 TXD */
  62         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
  63         mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
  64                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  65                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  66                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  67                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  68 }
  69
  70 static void setup_i2c(unsigned int port_number)
  71 {
  72         switch (port_number) {
  73         case 0:
  74                 /* i2c1 SDA */
  75                 mxc_request_iomux(MX53_PIN_CSI0_D8,
  76                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  77                 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
  78                                 INPUT_CTL_PATH0);
  79                 mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
  80                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  81                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  82                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  83                 /* i2c1 SCL */
  84                 mxc_request_iomux(MX53_PIN_CSI0_D9,
  85                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  86                 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
  87                                 INPUT_CTL_PATH0);
  88                 mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
  89                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  90                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  91                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  92                 break;
  93         case 1:
  94                 /* i2c2 SDA */
  95                 mxc_request_iomux(MX53_PIN_KEY_ROW3,
  96                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
  97                 mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
  98                                 INPUT_CTL_PATH0);
  99                 mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
 100                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 101                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 102                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 103
 104                 /* i2c2 SCL */
 105                 mxc_request_iomux(MX53_PIN_KEY_COL3,
 106                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
 107                 mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
 108                                 INPUT_CTL_PATH0);
 109                 mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
 110                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 111                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 112                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 113                 break;
 114         default:
 115                 printf("Warning: Wrong I2C port number\n");
 116                 break;
 117         }
 118 }
 119
 120 void power_init(void)
 121 {
 122         unsigned int val;
 123         struct pmic *p;
 124
 125         pmic_init();
 126         p = get_pmic();
 127
 128         /* Set VDDA to 1.25V */
 129         pmic_reg_read(p, REG_SW_2, &val);
 130         val &= ~SWX_OUT_MASK;
 131         val |= SWX_OUT_1_25;
 132         pmic_reg_write(p, REG_SW_2, val);
 133
 134         /*
 135          * Need increase VCC and VDDA to 1.3V
 136          * according to MX53 IC TO2 datasheet.
 137          */
 138         if (is_soc_rev(CHIP_REV_2_0) == 0) {
 139                 /* Set VCC to 1.3V for TO2 */
 140                 pmic_reg_read(p, REG_SW_1, &val);
 141                 val &= ~SWX_OUT_MASK;
 142                 val |= SWX_OUT_1_30;
 143                 pmic_reg_write(p, REG_SW_1, val);
 144
 145                 /* Set VDDA to 1.3V for TO2 */
 146                 pmic_reg_read(p, REG_SW_2, &val);
 147                 val &= ~SWX_OUT_MASK;
 148                 val |= SWX_OUT_1_30;
 149                 pmic_reg_write(p, REG_SW_2, val);
 150         }
 151 }
 152
 153 static void setup_iomux_fec(void)
 154 {
 155         /*FEC_MDIO*/
 156         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
 157         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
 158                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 159                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 160                                 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
 161         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
 162
 163         /*FEC_MDC*/
 164         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
 165         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
 166
 167         /* FEC RXD1 */
 168         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
 169         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
 170                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 171
 172         /* FEC RXD0 */
 173         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 174         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
 175                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 176
 177          /* FEC TXD1 */
 178         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 179         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 180
 181         /* FEC TXD0 */
 182         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 183         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 184
 185         /* FEC TX_EN */
 186         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 187         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 188
 189         /* FEC TX_CLK */
 190         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 191         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
 192                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 193
 194         /* FEC RX_ER */
 195         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 196         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
 197                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 198
 199         /* FEC CRS */
 200         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 201         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
 202                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 203 }
 204
 205 #ifdef CONFIG_FSL_ESDHC
 206 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 207         {MMC_SDHC1_BASE_ADDR, 1},
 208         {MMC_SDHC3_BASE_ADDR, 1},
 209 };
 210
 211 int board_mmc_getcd(struct mmc *mmc)
 212 {
 213         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 214         int ret;
 215
 216         mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
 217         mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
 218
 219         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 220                 ret = !gpio_get_value(77); /* GPIO3_13 */
 221         else
 222                 ret = !gpio_get_value(75); /* GPIO3_11 */
 223
 224         return ret;
 225 }
 226
 227 int board_mmc_init(bd_t *bis)
 228 {
 229         u32 index;
 230         s32 status = 0;
 231
 232         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 233                 switch (index) {
 234                 case 0:
 235                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 236                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 237                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 238                                                 IOMUX_CONFIG_ALT0);
 239                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 240                                                 IOMUX_CONFIG_ALT0);
 241                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 242                                                 IOMUX_CONFIG_ALT0);
 243                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 244                                                 IOMUX_CONFIG_ALT0);
 245                         mxc_request_iomux(MX53_PIN_EIM_DA13,
 246                                                 IOMUX_CONFIG_ALT1);
 247
 248                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 249                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 250                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 251                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 252                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 253                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 254                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 255                                 PAD_CTL_DRV_HIGH);
 256                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 257                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 258                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 259                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 260                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 261                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 262                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 263                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 264                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 265                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 266                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 267                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 268                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 269                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 270                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 271                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 272                         break;
 273                 case 1:
 274                         mxc_request_iomux(MX53_PIN_ATA_RESET_B,
 275                                                 IOMUX_CONFIG_ALT2);
 276                         mxc_request_iomux(MX53_PIN_ATA_IORDY,
 277                                                 IOMUX_CONFIG_ALT2);
 278                         mxc_request_iomux(MX53_PIN_ATA_DATA8,
 279                                                 IOMUX_CONFIG_ALT4);
 280                         mxc_request_iomux(MX53_PIN_ATA_DATA9,
 281                                                 IOMUX_CONFIG_ALT4);
 282                         mxc_request_iomux(MX53_PIN_ATA_DATA10,
 283                                                 IOMUX_CONFIG_ALT4);
 284                         mxc_request_iomux(MX53_PIN_ATA_DATA11,
 285                                                 IOMUX_CONFIG_ALT4);
 286                         mxc_request_iomux(MX53_PIN_ATA_DATA0,
 287                                                 IOMUX_CONFIG_ALT4);
 288                         mxc_request_iomux(MX53_PIN_ATA_DATA1,
 289                                                 IOMUX_CONFIG_ALT4);
 290                         mxc_request_iomux(MX53_PIN_ATA_DATA2,
 291                                                 IOMUX_CONFIG_ALT4);
 292                         mxc_request_iomux(MX53_PIN_ATA_DATA3,
 293                                                 IOMUX_CONFIG_ALT4);
 294                         mxc_request_iomux(MX53_PIN_EIM_DA11,
 295                                                 IOMUX_CONFIG_ALT1);
 296
 297                         mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
 298                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 299                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 300                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 301                         mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
 302                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 303                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 304                                 PAD_CTL_DRV_HIGH);
 305                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
 306                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 307                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 308                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 309                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
 310                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 311                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 312                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 313                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
 314                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 315                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 316                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 317                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
 318                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 319                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 320                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 321                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
 322                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 323                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 324                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 325                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
 326                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 327                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 328                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 329                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
 330                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 331                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 332                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 333                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
 334                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 335                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 336                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 337
 338                         break;
 339                 default:
 340                         printf("Warning: you configured more ESDHC controller"
 341                                 "(%d) as supported by the board(2)\n",
 342                                 CONFIG_SYS_FSL_ESDHC_NUM);
 343                         return status;
 344                 }
 345                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 346         }
 347
 348         return status;
 349 }
 350 #endif
 351
 352 int board_early_init_f(void)
 353 {
 354         setup_iomux_uart();
 355         setup_iomux_fec();
 356
 357         return 0;
 358 }
 359
 360 int board_init(void)
 361 {
 362         /* address of boot parameters */
 363         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 364
 365         return 0;
 366 }
 367
 368 int board_late_init(void)
 369 {
 370         setup_i2c(1);
 371         power_init();
 372
 373         return 0;
 374 }
 375
 376 int checkboard(void)
 377 {
 378         puts("Board: MX53EVK\n");
 379
 380         return 0;
 381 }