board/freescale/mx53evk/mx53evk.c

   1 /*
   2  * (C) Copyright 2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/clock.h>
  30 #include <asm/arch/iomux.h>
  31 #include <asm/errno.h>
  32 #include <asm/imx-common/boot_mode.h>
  33 #include <netdev.h>
  34 #include <i2c.h>
  35 #include <mmc.h>
  36 #include <fsl_esdhc.h>
  37 #include <pmic.h>
  38 #include <fsl_pmic.h>
  39 #include <asm/gpio.h>
  40 #include <mc13892.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 int dram_init(void)
  45 {
  46         /* dram_init must store complete ramsize in gd->ram_size */
  47         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  48                                 PHYS_SDRAM_1_SIZE);
  49         return 0;
  50 }
  51
  52 static void setup_iomux_uart(void)
  53 {
  54         /* UART1 RXD */
  55         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
  56         mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
  57                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  58                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  59                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  60                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  61         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
  62
  63         /* UART1 TXD */
  64         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
  65         mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
  66                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  67                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  68                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  69                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  70 }
  71
  72 static void setup_i2c(unsigned int port_number)
  73 {
  74         switch (port_number) {
  75         case 0:
  76                 /* i2c1 SDA */
  77                 mxc_request_iomux(MX53_PIN_CSI0_D8,
  78                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  79                 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
  80                                 INPUT_CTL_PATH0);
  81                 mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
  82                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  83                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  84                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  85                 /* i2c1 SCL */
  86                 mxc_request_iomux(MX53_PIN_CSI0_D9,
  87                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  88                 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
  89                                 INPUT_CTL_PATH0);
  90                 mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
  91                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  92                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  93                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  94                 break;
  95         case 1:
  96                 /* i2c2 SDA */
  97                 mxc_request_iomux(MX53_PIN_KEY_ROW3,
  98                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
  99                 mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
 100                                 INPUT_CTL_PATH0);
 101                 mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
 102                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 103                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 104                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 105
 106                 /* i2c2 SCL */
 107                 mxc_request_iomux(MX53_PIN_KEY_COL3,
 108                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
 109                 mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
 110                                 INPUT_CTL_PATH0);
 111                 mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
 112                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 113                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 114                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 115                 break;
 116         default:
 117                 printf("Warning: Wrong I2C port number\n");
 118                 break;
 119         }
 120 }
 121
 122 void power_init(void)
 123 {
 124         unsigned int val;
 125         struct pmic *p;
 126
 127         pmic_init();
 128         p = get_pmic();
 129
 130         /* Set VDDA to 1.25V */
 131         pmic_reg_read(p, REG_SW_2, &val);
 132         val &= ~SWX_OUT_MASK;
 133         val |= SWX_OUT_1_25;
 134         pmic_reg_write(p, REG_SW_2, val);
 135
 136         /*
 137          * Need increase VCC and VDDA to 1.3V
 138          * according to MX53 IC TO2 datasheet.
 139          */
 140         if (is_soc_rev(CHIP_REV_2_0) == 0) {
 141                 /* Set VCC to 1.3V for TO2 */
 142                 pmic_reg_read(p, REG_SW_1, &val);
 143                 val &= ~SWX_OUT_MASK;
 144                 val |= SWX_OUT_1_30;
 145                 pmic_reg_write(p, REG_SW_1, val);
 146
 147                 /* Set VDDA to 1.3V for TO2 */
 148                 pmic_reg_read(p, REG_SW_2, &val);
 149                 val &= ~SWX_OUT_MASK;
 150                 val |= SWX_OUT_1_30;
 151                 pmic_reg_write(p, REG_SW_2, val);
 152         }
 153 }
 154
 155 static void setup_iomux_fec(void)
 156 {
 157         /*FEC_MDIO*/
 158         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
 159         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
 160                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 161                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 162                                 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
 163         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
 164
 165         /*FEC_MDC*/
 166         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
 167         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
 168
 169         /* FEC RXD1 */
 170         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
 171         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
 172                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 173
 174         /* FEC RXD0 */
 175         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 176         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
 177                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 178
 179          /* FEC TXD1 */
 180         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 181         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 182
 183         /* FEC TXD0 */
 184         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 185         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 186
 187         /* FEC TX_EN */
 188         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 189         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 190
 191         /* FEC TX_CLK */
 192         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 193         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
 194                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 195
 196         /* FEC RX_ER */
 197         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 198         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
 199                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 200
 201         /* FEC CRS */
 202         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 203         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
 204                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 205 }
 206
 207 #ifdef CONFIG_FSL_ESDHC
 208 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 209         {MMC_SDHC1_BASE_ADDR},
 210         {MMC_SDHC3_BASE_ADDR},
 211 };
 212
 213 int board_mmc_getcd(struct mmc *mmc)
 214 {
 215         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 216         int ret;
 217
 218         mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
 219         gpio_direction_input(IMX_GPIO_NR(3, 11));
 220         mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
 221         gpio_direction_input(IMX_GPIO_NR(3, 13));
 222
 223         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 224                 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
 225         else
 226                 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
 227
 228         return ret;
 229 }
 230
 231 int board_mmc_init(bd_t *bis)
 232 {
 233         u32 index;
 234         s32 status = 0;
 235
 236         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 237         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 238
 239         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 240                 switch (index) {
 241                 case 0:
 242                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 243                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 244                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 245                                                 IOMUX_CONFIG_ALT0);
 246                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 247                                                 IOMUX_CONFIG_ALT0);
 248                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 249                                                 IOMUX_CONFIG_ALT0);
 250                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 251                                                 IOMUX_CONFIG_ALT0);
 252                         mxc_request_iomux(MX53_PIN_EIM_DA13,
 253                                                 IOMUX_CONFIG_ALT1);
 254
 255                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 256                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 257                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 258                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 259                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 260                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 261                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 262                                 PAD_CTL_DRV_HIGH);
 263                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 264                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 265                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 266                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 267                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 268                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 269                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 270                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 271                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 272                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 273                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 274                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 275                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 276                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 277                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 278                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 279                         break;
 280                 case 1:
 281                         mxc_request_iomux(MX53_PIN_ATA_RESET_B,
 282                                                 IOMUX_CONFIG_ALT2);
 283                         mxc_request_iomux(MX53_PIN_ATA_IORDY,
 284                                                 IOMUX_CONFIG_ALT2);
 285                         mxc_request_iomux(MX53_PIN_ATA_DATA8,
 286                                                 IOMUX_CONFIG_ALT4);
 287                         mxc_request_iomux(MX53_PIN_ATA_DATA9,
 288                                                 IOMUX_CONFIG_ALT4);
 289                         mxc_request_iomux(MX53_PIN_ATA_DATA10,
 290                                                 IOMUX_CONFIG_ALT4);
 291                         mxc_request_iomux(MX53_PIN_ATA_DATA11,
 292                                                 IOMUX_CONFIG_ALT4);
 293                         mxc_request_iomux(MX53_PIN_ATA_DATA0,
 294                                                 IOMUX_CONFIG_ALT4);
 295                         mxc_request_iomux(MX53_PIN_ATA_DATA1,
 296                                                 IOMUX_CONFIG_ALT4);
 297                         mxc_request_iomux(MX53_PIN_ATA_DATA2,
 298                                                 IOMUX_CONFIG_ALT4);
 299                         mxc_request_iomux(MX53_PIN_ATA_DATA3,
 300                                                 IOMUX_CONFIG_ALT4);
 301                         mxc_request_iomux(MX53_PIN_EIM_DA11,
 302                                                 IOMUX_CONFIG_ALT1);
 303
 304                         mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
 305                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 306                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 307                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 308                         mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
 309                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 310                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 311                                 PAD_CTL_DRV_HIGH);
 312                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
 313                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 314                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 315                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 316                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
 317                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 318                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 319                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 320                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
 321                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 322                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 323                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 324                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
 325                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 326                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 327                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 328                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
 329                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 330                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 331                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 332                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
 333                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 334                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 335                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 336                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
 337                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 338                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 339                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 340                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
 341                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 342                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 343                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 344
 345                         break;
 346                 default:
 347                         printf("Warning: you configured more ESDHC controller"
 348                                 "(%d) as supported by the board(2)\n",
 349                                 CONFIG_SYS_FSL_ESDHC_NUM);
 350                         return status;
 351                 }
 352                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 353         }
 354
 355         return status;
 356 }
 357 #endif
 358
 359 int board_early_init_f(void)
 360 {
 361         setup_iomux_uart();
 362         setup_iomux_fec();
 363
 364         return 0;
 365 }
 366
 367 int board_init(void)
 368 {
 369         /* address of boot parameters */
 370         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 371
 372         return 0;
 373 }
 374
 375 #ifdef CONFIG_CMD_BMODE
 376 static const struct boot_mode board_boot_modes[] = {
 377         /* 4 bit bus width */
 378         {"mmc0",        MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
 379         {"mmc1",        MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
 380         {NULL,          0},
 381 };
 382 #endif
 383
 384 int board_late_init(void)
 385 {
 386         setup_i2c(1);
 387         power_init();
 388
 389 #ifdef CONFIG_CMD_BMODE
 390         add_board_boot_modes(board_boot_modes);
 391 #endif
 392         return 0;
 393 }
 394
 395 int checkboard(void)
 396 {
 397         puts("Board: MX53EVK\n");
 398
 399         return 0;
 400 }