board/freescale/mx53ard/mx53ard.c

   1 /*
   2  * (C) Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/errno.h>
  31 #include <netdev.h>
  32 #include <mmc.h>
  33 #include <fsl_esdhc.h>
  34 #include <mxc_gpio.h>
  35
  36 #define ETHERNET_INT            (1 * 32 + 31)  /* GPIO2_31 */
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 u32 get_board_rev(void)
  41 {
  42         return get_cpu_rev();
  43 }
  44
  45 int dram_init(void)
  46 {
  47         u32 size1, size2;
  48
  49         size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  50         size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  51
  52         gd->ram_size = size1 + size2;
  53
  54         return 0;
  55 }
  56 void dram_init_banksize(void)
  57 {
  58         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  59         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  60
  61         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  62         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  63 }
  64
  65 static void setup_iomux_uart(void)
  66 {
  67         /* UART1 RXD */
  68         mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
  69         mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
  70                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  71                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  72                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  73                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  74         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
  75
  76         /* UART1 TXD */
  77         mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
  78         mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
  79                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  80                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  81                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  82                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  83 }
  84
  85 #ifdef CONFIG_FSL_ESDHC
  86 struct fsl_esdhc_cfg esdhc_cfg[2] = {
  87         {MMC_SDHC1_BASE_ADDR, 1 },
  88         {MMC_SDHC2_BASE_ADDR, 1 },
  89 };
  90
  91 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
  92 {
  93         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  94
  95         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  96                 *cd = mxc_gpio_get(1); /*GPIO1_1*/
  97         else
  98                 *cd = mxc_gpio_get(4); /*GPIO1_4*/
  99
 100         return 0;
 101 }
 102
 103 int board_mmc_init(bd_t *bis)
 104 {
 105         u32 index;
 106         s32 status = 0;
 107
 108         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 109                 switch (index) {
 110                 case 0:
 111                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 112                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 113                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 114                                                 IOMUX_CONFIG_ALT0);
 115                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 116                                                 IOMUX_CONFIG_ALT0);
 117                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 118                                                 IOMUX_CONFIG_ALT0);
 119                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 120                                                 IOMUX_CONFIG_ALT0);
 121
 122                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
 123                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
 124                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
 125                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
 126                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
 127                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
 128                         break;
 129                 case 1:
 130                         mxc_request_iomux(MX53_PIN_SD2_CMD,
 131                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 132                         mxc_request_iomux(MX53_PIN_SD2_CLK,
 133                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 134                         mxc_request_iomux(MX53_PIN_SD2_DATA0,
 135                                                 IOMUX_CONFIG_ALT0);
 136                         mxc_request_iomux(MX53_PIN_SD2_DATA1,
 137                                                 IOMUX_CONFIG_ALT0);
 138                         mxc_request_iomux(MX53_PIN_SD2_DATA2,
 139                                                 IOMUX_CONFIG_ALT0);
 140                         mxc_request_iomux(MX53_PIN_SD2_DATA3,
 141                                                 IOMUX_CONFIG_ALT0);
 142                         mxc_request_iomux(MX53_PIN_ATA_DATA12,
 143                                                 IOMUX_CONFIG_ALT2);
 144                         mxc_request_iomux(MX53_PIN_ATA_DATA13,
 145                                                 IOMUX_CONFIG_ALT2);
 146                         mxc_request_iomux(MX53_PIN_ATA_DATA14,
 147                                                 IOMUX_CONFIG_ALT2);
 148                         mxc_request_iomux(MX53_PIN_ATA_DATA15,
 149                                                 IOMUX_CONFIG_ALT2);
 150
 151                         mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
 152                         mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
 153                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
 154                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
 155                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
 156                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
 157                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
 158                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
 159                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
 160                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
 161                         break;
 162                 default:
 163                         printf("Warning: you configured more ESDHC controller"
 164                                 "(%d) as supported by the board(2)\n",
 165                                 CONFIG_SYS_FSL_ESDHC_NUM);
 166                         return status;
 167                 }
 168                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 169         }
 170
 171         return status;
 172 }
 173 #endif
 174
 175 static void weim_smc911x_iomux(void)
 176 {
 177         /* ETHERNET_INT as GPIO2_31 */
 178         mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
 179         mxc_gpio_direction(ETHERNET_INT, MXC_GPIO_DIRECTION_IN);
 180
 181         /* Data bus */
 182         mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0);
 183         mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
 184
 185         mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0);
 186         mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
 187
 188         mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0);
 189         mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
 190
 191         mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0);
 192         mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
 193
 194         mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0);
 195         mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
 196
 197         mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0);
 198         mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
 199
 200         mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0);
 201         mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
 202
 203         mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0);
 204         mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
 205
 206         mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0);
 207         mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
 208
 209         mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0);
 210         mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
 211
 212         mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0);
 213         mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
 214
 215         mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0);
 216         mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
 217
 218         mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0);
 219         mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
 220
 221         mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0);
 222         mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
 223
 224         mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0);
 225         mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
 226
 227         mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0);
 228         mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
 229
 230         /* Address lines */
 231         mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
 232         mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
 233
 234         mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
 235         mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
 236
 237         mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
 238         mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
 239
 240         mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
 241         mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
 242
 243         mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
 244         mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
 245
 246         mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
 247         mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
 248
 249         mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
 250         mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
 251
 252         /* other EIM signals for ethernet */
 253         mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0);
 254         mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0);
 255         mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
 256 }
 257
 258 static void weim_cs1_settings(void)
 259 {
 260         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 261
 262         writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
 263         writel(0x0, &weim_regs->cs1gcr2);
 264         writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
 265         writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
 266         writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
 267         writel(0x0, &weim_regs->cs1wcr2);
 268         writel(0x0, &weim_regs->wcr);
 269
 270         set_chipselect_size(CS0_64M_CS1_64M);
 271 }
 272
 273 int board_early_init_f(void)
 274 {
 275         setup_iomux_uart();
 276         return 0;
 277 }
 278
 279 int board_init(void)
 280 {
 281         gd->bd->bi_arch_number = MACH_TYPE_MX53_ARD;
 282         /* address of boot parameters */
 283         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 284
 285         return 0;
 286 }
 287
 288 int board_eth_init(bd_t *bis)
 289 {
 290         int rc = 0;
 291
 292         weim_smc911x_iomux();
 293         weim_cs1_settings();
 294
 295 #ifdef CONFIG_SMC911X
 296         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 297 #endif
 298         return rc;
 299 }
 300
 301 int checkboard(void)
 302 {
 303         puts("Board: MX53ARD\n");
 304
 305         return 0;
 306 }