2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/mx51_pins.h>
27 #include <asm/arch/iomux.h>
28 #include <asm/errno.h>
31 #include <fsl_esdhc.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 static u32 system_rev;
37 struct io_board_ctrl *mx51_io_board;
39 #ifdef CONFIG_FSL_ESDHC
40 struct fsl_esdhc_cfg esdhc_cfg[2] = {
41 {MMC_SDHC1_BASE_ADDR, 1, 1},
42 {MMC_SDHC2_BASE_ADDR, 1, 1},
46 u32 get_board_rev(void)
51 static inline void set_board_rev(int rev)
53 system_rev |= (rev & 0xF) << 8;
56 inline int is_soc_rev(int rev)
58 return (system_rev & 0xFF) - rev;
63 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
64 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
69 static void setup_iomux_uart(void)
71 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
72 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
74 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
75 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
76 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
77 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
78 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
79 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
80 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
81 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
84 static void setup_expio(void)
87 struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
88 struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR;
91 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
92 writel(0x00410089, &pweim[5].csgcr1);
93 writel(0x00000002, &pweim[5].csgcr2);
95 /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
96 writel(0x32260000, &pweim[5].csrcr1);
99 writel(0x00000000, &pweim[5].csrcr2);
102 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
105 writel(0x72080F00, &pweim[5].cswcr1);
107 mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR +
109 if ((readw(&mx51_io_board->id1) == 0xAAAA) &&
110 (readw(&mx51_io_board->id2) == 0x5555)) {
111 if (is_soc_rev(CHIP_REV_2_0) < 0) {
112 reg = readl(&pclkctl->cbcdr);
113 reg = (reg & (~0x70000)) | 0x30000;
114 writel(reg, &pclkctl->cbcdr);
115 /* make sure divider effective */
116 while (readl(&pclkctl->cdhipr) != 0)
118 writel(0x0, &pclkctl->ccdr);
122 writel(0x00410089, &pweim[1].csgcr1);
123 writel(0x00000002, &pweim[1].csgcr2);
124 /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
125 writel(0x32260000, &pweim[1].csrcr1);
127 writel(0x00000000, &pweim[1].csrcr2);
129 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
130 * WEN=0, WCSA=0, WCSN=0
132 writel(0x72080F00, &pweim[1].cswcr1);
133 mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR +
137 /* Reset interrupt status reg */
138 writew(0x1F, &(mx51_io_board->int_rest));
139 writew(0x00, &(mx51_io_board->int_rest));
140 writew(0xFFFF, &(mx51_io_board->int_mask));
142 /* Reset the XUART and Ethernet controllers */
143 reg = readw(&(mx51_io_board->sw_reset));
145 writew(reg, &(mx51_io_board->sw_reset));
147 writew(reg, &(mx51_io_board->sw_reset));
150 static void setup_iomux_fec(void)
153 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
154 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
157 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
158 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
161 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
162 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
165 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
166 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
169 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
170 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
173 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
174 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
177 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
178 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
181 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
182 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
185 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
186 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
189 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
190 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
193 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
194 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
197 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
198 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
201 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
202 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
205 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
206 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
209 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
210 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
213 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
214 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
217 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
218 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
221 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
222 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
225 #ifdef CONFIG_FSL_ESDHC
226 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
228 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
230 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
231 *cd = readl(GPIO1_BASE_ADDR) & 0x01;
233 *cd = readl(GPIO1_BASE_ADDR) & 0x40;
238 int board_mmc_init(bd_t *bis)
243 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
247 mxc_request_iomux(MX51_PIN_SD1_CMD,
248 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
249 mxc_request_iomux(MX51_PIN_SD1_CLK,
250 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
251 mxc_request_iomux(MX51_PIN_SD1_DATA0,
252 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
253 mxc_request_iomux(MX51_PIN_SD1_DATA1,
254 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
255 mxc_request_iomux(MX51_PIN_SD1_DATA2,
256 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
257 mxc_request_iomux(MX51_PIN_SD1_DATA3,
258 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
259 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
260 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
261 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
263 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
264 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
265 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
266 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
268 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
269 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
270 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
271 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
273 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
274 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
275 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
276 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
278 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
279 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
280 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
281 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
283 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
284 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
285 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
286 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
288 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
289 mxc_request_iomux(MX51_PIN_GPIO1_0,
290 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
291 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
293 mxc_request_iomux(MX51_PIN_GPIO1_1,
294 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
295 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
299 mxc_request_iomux(MX51_PIN_SD2_CMD,
300 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
301 mxc_request_iomux(MX51_PIN_SD2_CLK,
302 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
303 mxc_request_iomux(MX51_PIN_SD2_DATA0,
305 mxc_request_iomux(MX51_PIN_SD2_DATA1,
307 mxc_request_iomux(MX51_PIN_SD2_DATA2,
309 mxc_request_iomux(MX51_PIN_SD2_DATA3,
311 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
312 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
314 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
315 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
317 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
318 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
320 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
321 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
323 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
324 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
326 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
327 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
329 mxc_request_iomux(MX51_PIN_SD2_CMD,
330 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
331 mxc_request_iomux(MX51_PIN_GPIO1_6,
332 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
333 mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
335 mxc_request_iomux(MX51_PIN_GPIO1_5,
336 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
337 mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
341 printf("Warning: you configured more ESDHC controller"
342 "(%d) as supported by the board(2)\n",
343 CONFIG_SYS_FSL_ESDHC_NUM);
346 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
354 system_rev = get_cpu_rev();
356 gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
357 /* address of boot parameters */
358 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
368 puts("Board: MX51EVK ");
370 switch (system_rev & 0xff) {
389 switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {