2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/iomux.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
34 #include <fsl_esdhc.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 #ifdef CONFIG_FSL_ESDHC
42 struct fsl_esdhc_cfg esdhc_cfg[2] = {
43 {MMC_SDHC1_BASE_ADDR, 1},
44 {MMC_SDHC2_BASE_ADDR, 1},
50 /* dram_init must store complete ramsize in gd->ram_size */
51 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
56 static void setup_iomux_uart(void)
58 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
59 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
61 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
62 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
63 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
64 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
65 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
66 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
67 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
68 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
71 static void setup_iomux_fec(void)
74 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
75 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
78 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
79 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
82 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
83 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
86 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
87 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
90 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
91 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
94 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
95 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
98 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
99 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
102 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
103 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
106 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
107 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
110 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
111 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
114 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
115 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
118 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
119 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
122 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
123 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
126 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
127 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
130 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
131 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
134 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
135 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
138 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
139 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
142 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
143 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
146 #ifdef CONFIG_MXC_SPI
147 static void setup_iomux_spi(void)
149 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
150 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
151 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
153 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
154 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
155 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
157 /* de-select SS1 of instance: ecspi1. */
158 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
159 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
161 /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
162 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
163 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
165 /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
166 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
167 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
169 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
170 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
171 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
175 static void power_init(void)
178 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
184 /* Write needed to Power Gate 2 register */
185 pmic_reg_read(p, REG_POWER_MISC, &val);
187 pmic_reg_write(p, REG_POWER_MISC, val);
189 /* Externally powered */
190 pmic_reg_read(p, REG_CHARGE, &val);
191 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
192 pmic_reg_write(p, REG_CHARGE, val);
194 /* power up the system first */
195 pmic_reg_write(p, REG_POWER_MISC, PWUP);
197 /* Set core voltage to 1.1V */
198 pmic_reg_read(p, REG_SW_0, &val);
199 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
200 pmic_reg_write(p, REG_SW_0, val);
202 /* Setup VCC (SW2) to 1.25 */
203 pmic_reg_read(p, REG_SW_1, &val);
204 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
205 pmic_reg_write(p, REG_SW_1, val);
207 /* Setup 1V2_DIG1 (SW3) to 1.25 */
208 pmic_reg_read(p, REG_SW_2, &val);
209 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
210 pmic_reg_write(p, REG_SW_2, val);
213 /* Raise the core frequency to 800MHz */
214 writel(0x0, &mxc_ccm->cacrr);
216 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
217 /* Setup the switcher mode for SW1 & SW2*/
218 pmic_reg_read(p, REG_SW_4, &val);
219 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
220 (SWMODE_MASK << SWMODE2_SHIFT)));
221 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
222 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
223 pmic_reg_write(p, REG_SW_4, val);
225 /* Setup the switcher mode for SW3 & SW4 */
226 pmic_reg_read(p, REG_SW_5, &val);
227 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
228 (SWMODE_MASK << SWMODE4_SHIFT)));
229 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
230 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
231 pmic_reg_write(p, REG_SW_5, val);
233 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
234 pmic_reg_read(p, REG_SETTING_0, &val);
235 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
236 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
237 pmic_reg_write(p, REG_SETTING_0, val);
239 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
240 pmic_reg_read(p, REG_SETTING_1, &val);
241 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
242 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
243 pmic_reg_write(p, REG_SETTING_1, val);
245 /* Configure VGEN3 and VCAM regulators to use external PNP */
246 val = VGEN3CONFIG | VCAMCONFIG;
247 pmic_reg_write(p, REG_MODE_1, val);
250 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
251 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
252 VVIDEOEN | VAUDIOEN | VSDEN;
253 pmic_reg_write(p, REG_MODE_1, val);
255 mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
256 gpio_direction_output(46, 0);
260 gpio_set_value(46, 1);
263 #ifdef CONFIG_FSL_ESDHC
264 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
266 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
268 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
269 *cd = gpio_get_value(0);
271 *cd = gpio_get_value(6);
276 int board_mmc_init(bd_t *bis)
281 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
285 mxc_request_iomux(MX51_PIN_SD1_CMD,
286 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
287 mxc_request_iomux(MX51_PIN_SD1_CLK,
288 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
289 mxc_request_iomux(MX51_PIN_SD1_DATA0,
290 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
291 mxc_request_iomux(MX51_PIN_SD1_DATA1,
292 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
293 mxc_request_iomux(MX51_PIN_SD1_DATA2,
294 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
295 mxc_request_iomux(MX51_PIN_SD1_DATA3,
296 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
297 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
298 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
299 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
301 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
302 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
303 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
304 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
306 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
307 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
308 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
309 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
311 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
312 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
313 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
314 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
316 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
317 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
318 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
319 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
321 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
322 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
323 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
324 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
326 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
327 mxc_request_iomux(MX51_PIN_GPIO1_0,
328 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
329 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
331 mxc_request_iomux(MX51_PIN_GPIO1_1,
332 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
333 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
337 mxc_request_iomux(MX51_PIN_SD2_CMD,
338 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
339 mxc_request_iomux(MX51_PIN_SD2_CLK,
340 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
341 mxc_request_iomux(MX51_PIN_SD2_DATA0,
343 mxc_request_iomux(MX51_PIN_SD2_DATA1,
345 mxc_request_iomux(MX51_PIN_SD2_DATA2,
347 mxc_request_iomux(MX51_PIN_SD2_DATA3,
349 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
350 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
352 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
353 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
355 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
356 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
358 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
359 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
361 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
362 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
364 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
365 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
367 mxc_request_iomux(MX51_PIN_SD2_CMD,
368 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
369 mxc_request_iomux(MX51_PIN_GPIO1_6,
370 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
371 mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
373 mxc_request_iomux(MX51_PIN_GPIO1_5,
374 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
375 mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
379 printf("Warning: you configured more ESDHC controller"
380 "(%d) as supported by the board(2)\n",
381 CONFIG_SYS_FSL_ESDHC_NUM);
384 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
390 int board_early_init_f(void)
400 /* address of boot parameters */
401 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
406 #ifdef CONFIG_BOARD_LATE_INIT
407 int board_late_init(void)
409 #ifdef CONFIG_MXC_SPI
419 puts("Board: MX51EVK\n");