2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/mx5x_pins.h>
27 #include <asm/arch/iomux.h>
28 #include <asm/errno.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/crm_regs.h>
33 #include <fsl_esdhc.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 static u32 system_rev;
41 #ifdef CONFIG_FSL_ESDHC
42 struct fsl_esdhc_cfg esdhc_cfg[2] = {
43 {MMC_SDHC1_BASE_ADDR, 1},
44 {MMC_SDHC2_BASE_ADDR, 1},
48 u32 get_board_rev(void)
55 /* dram_init must store complete ramsize in gd->ram_size */
56 gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
61 static void setup_iomux_uart(void)
63 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
64 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
66 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
67 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
68 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
69 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
70 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
71 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
72 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
73 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
76 static void setup_iomux_fec(void)
79 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
80 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
83 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
84 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
87 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
88 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
91 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
92 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
95 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
96 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
99 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
100 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
103 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
104 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
107 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
108 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
111 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
112 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
115 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
116 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
119 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
120 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
123 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
124 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
127 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
128 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
131 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
132 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
135 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
136 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
139 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
140 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
143 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
144 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
147 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
148 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
151 #ifdef CONFIG_MXC_SPI
152 static void setup_iomux_spi(void)
154 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
155 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
156 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
158 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
159 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
160 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
162 /* de-select SS1 of instance: ecspi1. */
163 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
164 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
166 /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
167 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
168 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
170 /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
171 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
172 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
174 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
175 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
176 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
180 static void power_init(void)
184 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
186 /* Write needed to Power Gate 2 register */
187 val = pmic_reg_read(REG_POWER_MISC);
189 pmic_reg_write(REG_POWER_MISC, val);
191 /* Externally powered */
192 val = pmic_reg_read(REG_CHARGE);
193 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
194 pmic_reg_write(REG_CHARGE, val);
196 /* power up the system first */
197 pmic_reg_write(REG_POWER_MISC, PWUP);
199 /* Set core voltage to 1.1V */
200 val = pmic_reg_read(REG_SW_0);
201 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
202 pmic_reg_write(REG_SW_0, val);
204 /* Setup VCC (SW2) to 1.25 */
205 val = pmic_reg_read(REG_SW_1);
206 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
207 pmic_reg_write(REG_SW_1, val);
209 /* Setup 1V2_DIG1 (SW3) to 1.25 */
210 val = pmic_reg_read(REG_SW_2);
211 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
212 pmic_reg_write(REG_SW_2, val);
215 /* Raise the core frequency to 800MHz */
216 writel(0x0, &mxc_ccm->cacrr);
218 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
219 /* Setup the switcher mode for SW1 & SW2*/
220 val = pmic_reg_read(REG_SW_4);
221 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
222 (SWMODE_MASK << SWMODE2_SHIFT)));
223 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
224 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
225 pmic_reg_write(REG_SW_4, val);
227 /* Setup the switcher mode for SW3 & SW4 */
228 val = pmic_reg_read(REG_SW_5);
229 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
230 (SWMODE_MASK << SWMODE4_SHIFT)));
231 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
232 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
233 pmic_reg_write(REG_SW_5, val);
235 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
236 val = pmic_reg_read(REG_SETTING_0);
237 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
238 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
239 pmic_reg_write(REG_SETTING_0, val);
241 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
242 val = pmic_reg_read(REG_SETTING_1);
243 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
244 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
245 pmic_reg_write(REG_SETTING_1, val);
247 /* Configure VGEN3 and VCAM regulators to use external PNP */
248 val = VGEN3CONFIG | VCAMCONFIG;
249 pmic_reg_write(REG_MODE_1, val);
252 reg = readl(GPIO2_BASE_ADDR + 0x0);
253 reg &= ~0x4000; /* Lower reset line */
254 writel(reg, GPIO2_BASE_ADDR + 0x0);
256 reg = readl(GPIO2_BASE_ADDR + 0x4);
257 reg |= 0x4000; /* configure GPIO lines as output */
258 writel(reg, GPIO2_BASE_ADDR + 0x4);
260 /* Reset the ethernet controller over GPIO */
261 writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
263 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
264 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
265 VVIDEOEN | VAUDIOEN | VSDEN;
266 pmic_reg_write(REG_MODE_1, val);
270 reg = readl(GPIO2_BASE_ADDR + 0x0);
272 writel(reg, GPIO2_BASE_ADDR + 0x0);
275 #ifdef CONFIG_FSL_ESDHC
276 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
278 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
280 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
281 *cd = readl(GPIO1_BASE_ADDR) & 0x01;
283 *cd = readl(GPIO1_BASE_ADDR) & 0x40;
288 int board_mmc_init(bd_t *bis)
293 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
297 mxc_request_iomux(MX51_PIN_SD1_CMD,
298 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
299 mxc_request_iomux(MX51_PIN_SD1_CLK,
300 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
301 mxc_request_iomux(MX51_PIN_SD1_DATA0,
302 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
303 mxc_request_iomux(MX51_PIN_SD1_DATA1,
304 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
305 mxc_request_iomux(MX51_PIN_SD1_DATA2,
306 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
307 mxc_request_iomux(MX51_PIN_SD1_DATA3,
308 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
309 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
310 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
311 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
313 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
314 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
315 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
316 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
318 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
319 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
320 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
321 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
323 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
324 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
325 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
326 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
328 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
329 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
330 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
331 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
333 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
334 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
335 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
336 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
338 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
339 mxc_request_iomux(MX51_PIN_GPIO1_0,
340 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
341 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
343 mxc_request_iomux(MX51_PIN_GPIO1_1,
344 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
345 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
349 mxc_request_iomux(MX51_PIN_SD2_CMD,
350 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
351 mxc_request_iomux(MX51_PIN_SD2_CLK,
352 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
353 mxc_request_iomux(MX51_PIN_SD2_DATA0,
355 mxc_request_iomux(MX51_PIN_SD2_DATA1,
357 mxc_request_iomux(MX51_PIN_SD2_DATA2,
359 mxc_request_iomux(MX51_PIN_SD2_DATA3,
361 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
362 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
364 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
365 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
367 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
368 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
370 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
371 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
373 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
374 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
376 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
377 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
379 mxc_request_iomux(MX51_PIN_SD2_CMD,
380 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
381 mxc_request_iomux(MX51_PIN_GPIO1_6,
382 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
383 mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
385 mxc_request_iomux(MX51_PIN_GPIO1_5,
386 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
387 mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
391 printf("Warning: you configured more ESDHC controller"
392 "(%d) as supported by the board(2)\n",
393 CONFIG_SYS_FSL_ESDHC_NUM);
396 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
402 int board_early_init_f(void)
412 system_rev = get_cpu_rev();
414 gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
415 /* address of boot parameters */
416 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
421 #ifdef BOARD_LATE_INIT
422 int board_late_init(void)
424 #ifdef CONFIG_MXC_SPI
434 puts("Board: MX51EVK\n");