2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/iomux.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
34 #include <fsl_esdhc.h>
38 #include <usb/ehci-fsl.h>
40 #include <ipu_pixfmt.h>
42 #define MX51EVK_LCD_3V3 IMX_GPIO_NR(4, 9)
43 #define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10)
44 #define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4)
46 DECLARE_GLOBAL_DATA_PTR;
48 #ifdef CONFIG_FSL_ESDHC
49 struct fsl_esdhc_cfg esdhc_cfg[2] = {
50 {MMC_SDHC1_BASE_ADDR},
51 {MMC_SDHC2_BASE_ADDR},
57 /* dram_init must store complete ramsize in gd->ram_size */
58 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
63 static void setup_iomux_uart(void)
65 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
66 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
68 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
69 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
70 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
71 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
72 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
73 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
74 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
75 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
78 static void setup_iomux_fec(void)
81 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
82 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
85 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
86 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
89 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
90 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
93 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
94 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
97 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
98 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
101 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
102 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
105 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
106 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
109 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
110 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
113 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
114 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
117 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
118 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
121 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
122 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
125 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
126 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
129 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
130 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
133 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
134 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
137 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
138 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
141 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
142 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
145 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
146 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
149 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
150 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
153 #ifdef CONFIG_MXC_SPI
154 static void setup_iomux_spi(void)
156 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
157 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
158 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
160 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
161 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
162 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
164 /* de-select SS1 of instance: ecspi1. */
165 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
166 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
168 /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
169 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
170 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
172 /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
173 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
174 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
176 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
177 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
178 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
182 #ifdef CONFIG_USB_EHCI_MX5
183 #define MX51EVK_USBH1_HUB_RST IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */
184 #define MX51EVK_USBH1_STP IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */
185 #define MX51EVK_USB_CLK_EN_B IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */
186 #define MX51EVK_USB_PHY_RESET IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */
188 #define USBH1_PAD (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | \
189 PAD_CTL_100K_PU | PAD_CTL_PUE_PULL | \
190 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE)
191 #define GPIO_PAD (PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | \
193 #define NO_PAD (1 << 16)
195 static void setup_usb_h1(void)
197 setup_iomux_usb_h1();
199 /* GPIO_1_7 for USBH1 hub reset */
200 mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
201 mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD);
204 mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
205 mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD);
207 /* GPIO_2_5 for USB PHY reset */
208 mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
209 mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD);
212 int board_ehci_hcd_init(int port)
214 /* Set USBH1_STP to GPIO and toggle it */
215 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
216 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
218 gpio_direction_output(MX51EVK_USBH1_STP, 0);
219 gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
221 gpio_set_value(MX51EVK_USBH1_STP, 1);
223 /* Set back USBH1_STP to be function */
224 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
225 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
227 /* De-assert USB PHY RESETB */
228 gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
230 /* Drive USB_CLK_EN_B line low */
231 gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
234 gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
236 gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
241 static void power_init(void)
244 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
250 /* Write needed to Power Gate 2 register */
251 pmic_reg_read(p, REG_POWER_MISC, &val);
253 pmic_reg_write(p, REG_POWER_MISC, val);
255 /* Externally powered */
256 pmic_reg_read(p, REG_CHARGE, &val);
257 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
258 pmic_reg_write(p, REG_CHARGE, val);
260 /* power up the system first */
261 pmic_reg_write(p, REG_POWER_MISC, PWUP);
263 /* Set core voltage to 1.1V */
264 pmic_reg_read(p, REG_SW_0, &val);
265 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
266 pmic_reg_write(p, REG_SW_0, val);
268 /* Setup VCC (SW2) to 1.25 */
269 pmic_reg_read(p, REG_SW_1, &val);
270 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
271 pmic_reg_write(p, REG_SW_1, val);
273 /* Setup 1V2_DIG1 (SW3) to 1.25 */
274 pmic_reg_read(p, REG_SW_2, &val);
275 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
276 pmic_reg_write(p, REG_SW_2, val);
279 /* Raise the core frequency to 800MHz */
280 writel(0x0, &mxc_ccm->cacrr);
282 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
283 /* Setup the switcher mode for SW1 & SW2*/
284 pmic_reg_read(p, REG_SW_4, &val);
285 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
286 (SWMODE_MASK << SWMODE2_SHIFT)));
287 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
288 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
289 pmic_reg_write(p, REG_SW_4, val);
291 /* Setup the switcher mode for SW3 & SW4 */
292 pmic_reg_read(p, REG_SW_5, &val);
293 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
294 (SWMODE_MASK << SWMODE4_SHIFT)));
295 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
296 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
297 pmic_reg_write(p, REG_SW_5, val);
299 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
300 pmic_reg_read(p, REG_SETTING_0, &val);
301 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
302 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
303 pmic_reg_write(p, REG_SETTING_0, val);
305 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
306 pmic_reg_read(p, REG_SETTING_1, &val);
307 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
308 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
309 pmic_reg_write(p, REG_SETTING_1, val);
311 /* Configure VGEN3 and VCAM regulators to use external PNP */
312 val = VGEN3CONFIG | VCAMCONFIG;
313 pmic_reg_write(p, REG_MODE_1, val);
316 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
317 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
318 VVIDEOEN | VAUDIOEN | VSDEN;
319 pmic_reg_write(p, REG_MODE_1, val);
321 mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
322 gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
326 gpio_set_value(IMX_GPIO_NR(2, 14), 1);
329 #ifdef CONFIG_FSL_ESDHC
330 int board_mmc_getcd(struct mmc *mmc)
332 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
335 mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
336 gpio_direction_input(IMX_GPIO_NR(1, 0));
337 mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
338 gpio_direction_input(IMX_GPIO_NR(1, 6));
340 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
341 ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
343 ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
348 int board_mmc_init(bd_t *bis)
353 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
357 mxc_request_iomux(MX51_PIN_SD1_CMD,
358 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
359 mxc_request_iomux(MX51_PIN_SD1_CLK,
360 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
361 mxc_request_iomux(MX51_PIN_SD1_DATA0,
362 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
363 mxc_request_iomux(MX51_PIN_SD1_DATA1,
364 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
365 mxc_request_iomux(MX51_PIN_SD1_DATA2,
366 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
367 mxc_request_iomux(MX51_PIN_SD1_DATA3,
368 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
369 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
370 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
371 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
373 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
374 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
375 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
376 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
378 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
379 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
380 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
381 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
383 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
384 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
385 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
386 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
388 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
389 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
390 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
391 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
393 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
394 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
395 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
396 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
398 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
399 mxc_request_iomux(MX51_PIN_GPIO1_0,
400 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
401 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
403 mxc_request_iomux(MX51_PIN_GPIO1_1,
404 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
405 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
409 mxc_request_iomux(MX51_PIN_SD2_CMD,
410 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
411 mxc_request_iomux(MX51_PIN_SD2_CLK,
412 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
413 mxc_request_iomux(MX51_PIN_SD2_DATA0,
415 mxc_request_iomux(MX51_PIN_SD2_DATA1,
417 mxc_request_iomux(MX51_PIN_SD2_DATA2,
419 mxc_request_iomux(MX51_PIN_SD2_DATA3,
421 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
422 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
424 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
425 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
427 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
428 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
430 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
431 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
433 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
434 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
436 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
437 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
439 mxc_request_iomux(MX51_PIN_SD2_CMD,
440 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
441 mxc_request_iomux(MX51_PIN_GPIO1_6,
442 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
443 mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
445 mxc_request_iomux(MX51_PIN_GPIO1_5,
446 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
447 mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
451 printf("Warning: you configured more ESDHC controller"
452 "(%d) as supported by the board(2)\n",
453 CONFIG_SYS_FSL_ESDHC_NUM);
456 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
462 static struct fb_videomode claa_wvga = {
463 .name = "CLAA07LC0ACW",
475 .vmode = FB_VMODE_NONINTERLACED
481 mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4);
483 /* Pad settings for MX51_PIN_DI2_DISP_CLK */
484 mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE |
485 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
486 PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW);
488 /* Turn on 3.3V voltage for LCD */
489 mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3);
490 gpio_direction_output(MX51EVK_LCD_3V3, 1);
492 /* Turn on 5V voltage for LCD */
493 mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3);
494 gpio_direction_output(MX51EVK_LCD_5V, 1);
496 /* Turn on GPIO backlight */
497 mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
498 mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
500 gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
503 void lcd_enable(void)
505 int ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
507 printf("LCD cannot be configured: %d\n", ret);
510 int board_early_init_f(void)
514 #ifdef CONFIG_USB_EHCI_MX5
524 /* address of boot parameters */
525 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
532 #ifdef CONFIG_BOARD_LATE_INIT
533 int board_late_init(void)
535 #ifdef CONFIG_MXC_SPI
545 * Do not overwrite the console
546 * Use always serial for U-Boot console
548 int overwrite_console(void)
555 puts("Board: MX51EVK\n");