USB: mx51evk: add end enable USB host support on port 1
[platform/kernel/u-boot.git] / board / freescale / mx51evk / mx51evk.c
1 /*
2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22
23 #include <common.h>
24 #include <asm/io.h>
25 #include <asm/gpio.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/iomux.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
32 #include <i2c.h>
33 #include <mmc.h>
34 #include <fsl_esdhc.h>
35 #include <pmic.h>
36 #include <fsl_pmic.h>
37 #include <mc13892.h>
38 #include <usb/ehci-fsl.h>
39
40 DECLARE_GLOBAL_DATA_PTR;
41
42 #ifdef CONFIG_FSL_ESDHC
43 struct fsl_esdhc_cfg esdhc_cfg[2] = {
44         {MMC_SDHC1_BASE_ADDR, 1},
45         {MMC_SDHC2_BASE_ADDR, 1},
46 };
47 #endif
48
49 int dram_init(void)
50 {
51         /* dram_init must store complete ramsize in gd->ram_size */
52         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
53                                 PHYS_SDRAM_1_SIZE);
54         return 0;
55 }
56
57 static void setup_iomux_uart(void)
58 {
59         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
60                         PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
61
62         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
63         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
64         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
65         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
66         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
67         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
68         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
69         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
70 }
71
72 static void setup_iomux_fec(void)
73 {
74         /*FEC_MDIO*/
75         mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
76         mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
77
78         /*FEC_MDC*/
79         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
80         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
81
82         /* FEC RDATA[3] */
83         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
84         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
85
86         /* FEC RDATA[2] */
87         mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
88         mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
89
90         /* FEC RDATA[1] */
91         mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
92         mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
93
94         /* FEC RDATA[0] */
95         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
96         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
97
98         /* FEC TDATA[3] */
99         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
100         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
101
102         /* FEC TDATA[2] */
103         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
104         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
105
106         /* FEC TDATA[1] */
107         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
108         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
109
110         /* FEC TDATA[0] */
111         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
112         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
113
114         /* FEC TX_EN */
115         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
116         mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
117
118         /* FEC TX_ER */
119         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
120         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
121
122         /* FEC TX_CLK */
123         mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
124         mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
125
126         /* FEC TX_COL */
127         mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
128         mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
129
130         /* FEC RX_CLK */
131         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
132         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
133
134         /* FEC RX_CRS */
135         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
136         mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
137
138         /* FEC RX_ER */
139         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
140         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
141
142         /* FEC RX_DV */
143         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
144         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
145 }
146
147 #ifdef CONFIG_MXC_SPI
148 static void setup_iomux_spi(void)
149 {
150         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
151         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
152         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
153
154         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
155         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
156         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
157
158         /* de-select SS1 of instance: ecspi1. */
159         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
160         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
161
162         /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
163         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
164         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
165
166         /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
167         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
168         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
169
170         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
171         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
172         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
173 }
174 #endif
175
176 #ifdef CONFIG_USB_EHCI_MX5
177 #define MX51EVK_USBH1_HUB_RST   IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */
178 #define MX51EVK_USBH1_STP       IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */
179 #define MX51EVK_USB_CLK_EN_B    IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */
180 #define MX51EVK_USB_PHY_RESET   IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */
181
182 #define USBH1_PAD       (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |          \
183                          PAD_CTL_100K_PU | PAD_CTL_PUE_PULL |           \
184                          PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE)
185 #define GPIO_PAD        (PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE |        \
186                          PAD_CTL_SRE_FAST)
187 #define NO_PAD          (1 << 16)
188
189 static void setup_usb_h1(void)
190 {
191         setup_iomux_usb_h1();
192
193         /* GPIO_1_7 for USBH1 hub reset */
194         mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
195         mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD);
196
197         /* GPIO_2_1 */
198         mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
199         mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD);
200
201         /* GPIO_2_5 for USB PHY reset */
202         mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
203         mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD);
204 }
205
206 void board_ehci_hcd_init(int port)
207 {
208         /* Set USBH1_STP to GPIO and toggle it */
209         mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
210         mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
211
212         gpio_direction_output(MX51EVK_USBH1_STP, 0);
213         gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
214         mdelay(10);
215         gpio_set_value(MX51EVK_USBH1_STP, 1);
216
217         /* Set back USBH1_STP to be function */
218         mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
219         mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
220
221         /* De-assert USB PHY RESETB */
222         gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
223
224         /* Drive USB_CLK_EN_B line low */
225         gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
226
227         /* Reset USB hub */
228         gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
229         mdelay(2);
230         gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
231 }
232 #endif
233
234 static void power_init(void)
235 {
236         unsigned int val;
237         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
238         struct pmic *p;
239
240         pmic_init();
241         p = get_pmic();
242
243         /* Write needed to Power Gate 2 register */
244         pmic_reg_read(p, REG_POWER_MISC, &val);
245         val &= ~PWGT2SPIEN;
246         pmic_reg_write(p, REG_POWER_MISC, val);
247
248         /* Externally powered */
249         pmic_reg_read(p, REG_CHARGE, &val);
250         val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
251         pmic_reg_write(p, REG_CHARGE, val);
252
253         /* power up the system first */
254         pmic_reg_write(p, REG_POWER_MISC, PWUP);
255
256         /* Set core voltage to 1.1V */
257         pmic_reg_read(p, REG_SW_0, &val);
258         val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
259         pmic_reg_write(p, REG_SW_0, val);
260
261         /* Setup VCC (SW2) to 1.25 */
262         pmic_reg_read(p, REG_SW_1, &val);
263         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
264         pmic_reg_write(p, REG_SW_1, val);
265
266         /* Setup 1V2_DIG1 (SW3) to 1.25 */
267         pmic_reg_read(p, REG_SW_2, &val);
268         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
269         pmic_reg_write(p, REG_SW_2, val);
270         udelay(50);
271
272         /* Raise the core frequency to 800MHz */
273         writel(0x0, &mxc_ccm->cacrr);
274
275         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
276         /* Setup the switcher mode for SW1 & SW2*/
277         pmic_reg_read(p, REG_SW_4, &val);
278         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
279                 (SWMODE_MASK << SWMODE2_SHIFT)));
280         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
281                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
282         pmic_reg_write(p, REG_SW_4, val);
283
284         /* Setup the switcher mode for SW3 & SW4 */
285         pmic_reg_read(p, REG_SW_5, &val);
286         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
287                 (SWMODE_MASK << SWMODE4_SHIFT)));
288         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
289                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
290         pmic_reg_write(p, REG_SW_5, val);
291
292         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
293         pmic_reg_read(p, REG_SETTING_0, &val);
294         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
295         val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
296         pmic_reg_write(p, REG_SETTING_0, val);
297
298         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
299         pmic_reg_read(p, REG_SETTING_1, &val);
300         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
301         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
302         pmic_reg_write(p, REG_SETTING_1, val);
303
304         /* Configure VGEN3 and VCAM regulators to use external PNP */
305         val = VGEN3CONFIG | VCAMCONFIG;
306         pmic_reg_write(p, REG_MODE_1, val);
307         udelay(200);
308
309         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
310         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
311                 VVIDEOEN | VAUDIOEN  | VSDEN;
312         pmic_reg_write(p, REG_MODE_1, val);
313
314         mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
315         gpio_direction_output(46, 0);
316
317         udelay(500);
318
319         gpio_set_value(46, 1);
320 }
321
322 #ifdef CONFIG_FSL_ESDHC
323 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
324 {
325         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
326
327         mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
328         mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
329
330         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
331                 *cd = gpio_get_value(0);
332         else
333                 *cd = gpio_get_value(6);
334
335         return 0;
336 }
337
338 int board_mmc_init(bd_t *bis)
339 {
340         u32 index;
341         s32 status = 0;
342
343         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
344                         index++) {
345                 switch (index) {
346                 case 0:
347                         mxc_request_iomux(MX51_PIN_SD1_CMD,
348                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
349                         mxc_request_iomux(MX51_PIN_SD1_CLK,
350                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
351                         mxc_request_iomux(MX51_PIN_SD1_DATA0,
352                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
353                         mxc_request_iomux(MX51_PIN_SD1_DATA1,
354                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
355                         mxc_request_iomux(MX51_PIN_SD1_DATA2,
356                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
357                         mxc_request_iomux(MX51_PIN_SD1_DATA3,
358                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
359                         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
360                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
361                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
362                                 PAD_CTL_PUE_PULL |
363                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
364                         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
365                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
366                                 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
367                                 PAD_CTL_PUE_PULL |
368                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
369                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
370                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
371                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
372                                 PAD_CTL_PUE_PULL |
373                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
374                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
375                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
376                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
377                                 PAD_CTL_PUE_PULL |
378                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
379                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
380                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
381                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
382                                 PAD_CTL_PUE_PULL |
383                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
384                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
385                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
386                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
387                                 PAD_CTL_PUE_PULL |
388                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
389                         mxc_request_iomux(MX51_PIN_GPIO1_0,
390                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
391                         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
392                                 PAD_CTL_HYS_ENABLE);
393                         mxc_request_iomux(MX51_PIN_GPIO1_1,
394                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
395                         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
396                                 PAD_CTL_HYS_ENABLE);
397                         break;
398                 case 1:
399                         mxc_request_iomux(MX51_PIN_SD2_CMD,
400                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
401                         mxc_request_iomux(MX51_PIN_SD2_CLK,
402                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
403                         mxc_request_iomux(MX51_PIN_SD2_DATA0,
404                                 IOMUX_CONFIG_ALT0);
405                         mxc_request_iomux(MX51_PIN_SD2_DATA1,
406                                 IOMUX_CONFIG_ALT0);
407                         mxc_request_iomux(MX51_PIN_SD2_DATA2,
408                                 IOMUX_CONFIG_ALT0);
409                         mxc_request_iomux(MX51_PIN_SD2_DATA3,
410                                 IOMUX_CONFIG_ALT0);
411                         mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
412                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
413                                 PAD_CTL_SRE_FAST);
414                         mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
415                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
416                                 PAD_CTL_SRE_FAST);
417                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
418                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
419                                 PAD_CTL_SRE_FAST);
420                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
421                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
422                                 PAD_CTL_SRE_FAST);
423                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
424                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
425                                 PAD_CTL_SRE_FAST);
426                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
427                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
428                                 PAD_CTL_SRE_FAST);
429                         mxc_request_iomux(MX51_PIN_SD2_CMD,
430                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
431                         mxc_request_iomux(MX51_PIN_GPIO1_6,
432                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
433                         mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
434                                 PAD_CTL_HYS_ENABLE);
435                         mxc_request_iomux(MX51_PIN_GPIO1_5,
436                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
437                         mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
438                                 PAD_CTL_HYS_ENABLE);
439                         break;
440                 default:
441                         printf("Warning: you configured more ESDHC controller"
442                                 "(%d) as supported by the board(2)\n",
443                                 CONFIG_SYS_FSL_ESDHC_NUM);
444                         return status;
445                 }
446                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
447         }
448         return status;
449 }
450 #endif
451
452 int board_early_init_f(void)
453 {
454         setup_iomux_uart();
455         setup_iomux_fec();
456 #ifdef CONFIG_USB_EHCI_MX5
457         setup_usb_h1();
458 #endif
459
460         return 0;
461 }
462
463 int board_init(void)
464 {
465         /* address of boot parameters */
466         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
467
468         return 0;
469 }
470
471 #ifdef CONFIG_BOARD_LATE_INIT
472 int board_late_init(void)
473 {
474 #ifdef CONFIG_MXC_SPI
475         setup_iomux_spi();
476         power_init();
477 #endif
478         return 0;
479 }
480 #endif
481
482 int checkboard(void)
483 {
484         puts("Board: MX51EVK\n");
485
486         return 0;
487 }