board/freescale/mx51evk/mx51evk.c

   1 /*
   2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/gpio.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/mx5x_pins.h>
  28 #include <asm/arch/iomux.h>
  29 #include <asm/errno.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <asm/arch/crm_regs.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/imx-common/mx5_video.h>
  34 #include <i2c.h>
  35 #include <mmc.h>
  36 #include <fsl_esdhc.h>
  37 #include <pmic.h>
  38 #include <fsl_pmic.h>
  39 #include <mc13892.h>
  40 #include <usb/ehci-fsl.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 #ifdef CONFIG_FSL_ESDHC
  45 struct fsl_esdhc_cfg esdhc_cfg[2] = {
  46         {MMC_SDHC1_BASE_ADDR},
  47         {MMC_SDHC2_BASE_ADDR},
  48 };
  49 #endif
  50
  51 int dram_init(void)
  52 {
  53         /* dram_init must store complete ramsize in gd->ram_size */
  54         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  55                                 PHYS_SDRAM_1_SIZE);
  56         return 0;
  57 }
  58
  59 u32 get_board_rev(void)
  60 {
  61         u32 rev = get_cpu_rev();
  62         if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
  63                 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
  64         return rev;
  65 }
  66
  67 static void setup_iomux_uart(void)
  68 {
  69         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
  70                         PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
  71
  72         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
  73         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
  74         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
  75         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
  76         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
  77         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
  78         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
  79         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
  80 }
  81
  82 static void setup_iomux_fec(void)
  83 {
  84         /*FEC_MDIO*/
  85         mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
  86         mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
  87
  88         /*FEC_MDC*/
  89         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
  90         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
  91
  92         /* FEC RDATA[3] */
  93         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
  94         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
  95
  96         /* FEC RDATA[2] */
  97         mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
  98         mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
  99
 100         /* FEC RDATA[1] */
 101         mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
 102         mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
 103
 104         /* FEC RDATA[0] */
 105         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
 106         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
 107
 108         /* FEC TDATA[3] */
 109         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
 110         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
 111
 112         /* FEC TDATA[2] */
 113         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
 114         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
 115
 116         /* FEC TDATA[1] */
 117         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
 118         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
 119
 120         /* FEC TDATA[0] */
 121         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
 122         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
 123
 124         /* FEC TX_EN */
 125         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
 126         mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
 127
 128         /* FEC TX_ER */
 129         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
 130         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
 131
 132         /* FEC TX_CLK */
 133         mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
 134         mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
 135
 136         /* FEC TX_COL */
 137         mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 138         mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 139
 140         /* FEC RX_CLK */
 141         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 142         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 143
 144         /* FEC RX_CRS */
 145         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
 146         mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
 147
 148         /* FEC RX_ER */
 149         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 150         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 151
 152         /* FEC RX_DV */
 153         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
 154         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
 155 }
 156
 157 #ifdef CONFIG_MXC_SPI
 158 static void setup_iomux_spi(void)
 159 {
 160         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 161         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 162         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
 163
 164         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 165         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 166         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
 167
 168         /* de-select SS1 of instance: ecspi1. */
 169         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
 170         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
 171
 172         /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
 173         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
 174         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
 175
 176         /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
 177         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
 178         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
 179
 180         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 181         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 182         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
 183 }
 184 #endif
 185
 186 #ifdef CONFIG_USB_EHCI_MX5
 187 #define MX51EVK_USBH1_HUB_RST   IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */
 188 #define MX51EVK_USBH1_STP       IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */
 189 #define MX51EVK_USB_CLK_EN_B    IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */
 190 #define MX51EVK_USB_PHY_RESET   IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */
 191
 192 #define USBH1_PAD       (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |          \
 193                          PAD_CTL_100K_PU | PAD_CTL_PUE_PULL |           \
 194                          PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE)
 195 #define GPIO_PAD        (PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE |        \
 196                          PAD_CTL_SRE_FAST)
 197 #define NO_PAD          (1 << 16)
 198
 199 static void setup_usb_h1(void)
 200 {
 201         setup_iomux_usb_h1();
 202
 203         /* GPIO_1_7 for USBH1 hub reset */
 204         mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
 205         mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD);
 206
 207         /* GPIO_2_1 */
 208         mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
 209         mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD);
 210
 211         /* GPIO_2_5 for USB PHY reset */
 212         mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
 213         mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD);
 214 }
 215
 216 int board_ehci_hcd_init(int port)
 217 {
 218         /* Set USBH1_STP to GPIO and toggle it */
 219         mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
 220         mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
 221
 222         gpio_direction_output(MX51EVK_USBH1_STP, 0);
 223         gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
 224         mdelay(10);
 225         gpio_set_value(MX51EVK_USBH1_STP, 1);
 226
 227         /* Set back USBH1_STP to be function */
 228         mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
 229         mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
 230
 231         /* De-assert USB PHY RESETB */
 232         gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
 233
 234         /* Drive USB_CLK_EN_B line low */
 235         gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
 236
 237         /* Reset USB hub */
 238         gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
 239         mdelay(2);
 240         gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
 241         return 0;
 242 }
 243 #endif
 244
 245 static void power_init(void)
 246 {
 247         unsigned int val;
 248         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 249         struct pmic *p;
 250
 251         pmic_init();
 252         p = get_pmic();
 253
 254         /* Write needed to Power Gate 2 register */
 255         pmic_reg_read(p, REG_POWER_MISC, &val);
 256         val &= ~PWGT2SPIEN;
 257         pmic_reg_write(p, REG_POWER_MISC, val);
 258
 259         /* Externally powered */
 260         pmic_reg_read(p, REG_CHARGE, &val);
 261         val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
 262         pmic_reg_write(p, REG_CHARGE, val);
 263
 264         /* power up the system first */
 265         pmic_reg_write(p, REG_POWER_MISC, PWUP);
 266
 267         /* Set core voltage to 1.1V */
 268         pmic_reg_read(p, REG_SW_0, &val);
 269         val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
 270         pmic_reg_write(p, REG_SW_0, val);
 271
 272         /* Setup VCC (SW2) to 1.25 */
 273         pmic_reg_read(p, REG_SW_1, &val);
 274         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 275         pmic_reg_write(p, REG_SW_1, val);
 276
 277         /* Setup 1V2_DIG1 (SW3) to 1.25 */
 278         pmic_reg_read(p, REG_SW_2, &val);
 279         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 280         pmic_reg_write(p, REG_SW_2, val);
 281         udelay(50);
 282
 283         /* Raise the core frequency to 800MHz */
 284         writel(0x0, &mxc_ccm->cacrr);
 285
 286         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
 287         /* Setup the switcher mode for SW1 & SW2*/
 288         pmic_reg_read(p, REG_SW_4, &val);
 289         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 290                 (SWMODE_MASK << SWMODE2_SHIFT)));
 291         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 292                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 293         pmic_reg_write(p, REG_SW_4, val);
 294
 295         /* Setup the switcher mode for SW3 & SW4 */
 296         pmic_reg_read(p, REG_SW_5, &val);
 297         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
 298                 (SWMODE_MASK << SWMODE4_SHIFT)));
 299         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
 300                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
 301         pmic_reg_write(p, REG_SW_5, val);
 302
 303         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
 304         pmic_reg_read(p, REG_SETTING_0, &val);
 305         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
 306         val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
 307         pmic_reg_write(p, REG_SETTING_0, val);
 308
 309         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
 310         pmic_reg_read(p, REG_SETTING_1, &val);
 311         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 312         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
 313         pmic_reg_write(p, REG_SETTING_1, val);
 314
 315         /* Configure VGEN3 and VCAM regulators to use external PNP */
 316         val = VGEN3CONFIG | VCAMCONFIG;
 317         pmic_reg_write(p, REG_MODE_1, val);
 318         udelay(200);
 319
 320         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 321         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 322                 VVIDEOEN | VAUDIOEN  | VSDEN;
 323         pmic_reg_write(p, REG_MODE_1, val);
 324
 325         mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
 326         gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
 327
 328         udelay(500);
 329
 330         gpio_set_value(IMX_GPIO_NR(2, 14), 1);
 331 }
 332
 333 #ifdef CONFIG_FSL_ESDHC
 334 int board_mmc_getcd(struct mmc *mmc)
 335 {
 336         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 337         int ret;
 338
 339         mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
 340         gpio_direction_input(IMX_GPIO_NR(1, 0));
 341         mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
 342         gpio_direction_input(IMX_GPIO_NR(1, 6));
 343
 344         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 345                 ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
 346         else
 347                 ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
 348
 349         return ret;
 350 }
 351
 352 int board_mmc_init(bd_t *bis)
 353 {
 354         u32 index;
 355         s32 status = 0;
 356
 357         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 358         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 359
 360         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 361                         index++) {
 362                 switch (index) {
 363                 case 0:
 364                         mxc_request_iomux(MX51_PIN_SD1_CMD,
 365                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 366                         mxc_request_iomux(MX51_PIN_SD1_CLK,
 367                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 368                         mxc_request_iomux(MX51_PIN_SD1_DATA0,
 369                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 370                         mxc_request_iomux(MX51_PIN_SD1_DATA1,
 371                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 372                         mxc_request_iomux(MX51_PIN_SD1_DATA2,
 373                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 374                         mxc_request_iomux(MX51_PIN_SD1_DATA3,
 375                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 376                         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 377                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 378                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 379                                 PAD_CTL_PUE_PULL |
 380                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 381                         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 382                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 383                                 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
 384                                 PAD_CTL_PUE_PULL |
 385                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 386                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 387                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 388                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 389                                 PAD_CTL_PUE_PULL |
 390                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 391                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 392                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 393                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 394                                 PAD_CTL_PUE_PULL |
 395                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 396                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 397                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 398                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 399                                 PAD_CTL_PUE_PULL |
 400                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 401                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 402                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 403                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
 404                                 PAD_CTL_PUE_PULL |
 405                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 406                         mxc_request_iomux(MX51_PIN_GPIO1_0,
 407                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 408                         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
 409                                 PAD_CTL_HYS_ENABLE);
 410                         mxc_request_iomux(MX51_PIN_GPIO1_1,
 411                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 412                         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 413                                 PAD_CTL_HYS_ENABLE);
 414                         break;
 415                 case 1:
 416                         mxc_request_iomux(MX51_PIN_SD2_CMD,
 417                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 418                         mxc_request_iomux(MX51_PIN_SD2_CLK,
 419                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 420                         mxc_request_iomux(MX51_PIN_SD2_DATA0,
 421                                 IOMUX_CONFIG_ALT0);
 422                         mxc_request_iomux(MX51_PIN_SD2_DATA1,
 423                                 IOMUX_CONFIG_ALT0);
 424                         mxc_request_iomux(MX51_PIN_SD2_DATA2,
 425                                 IOMUX_CONFIG_ALT0);
 426                         mxc_request_iomux(MX51_PIN_SD2_DATA3,
 427                                 IOMUX_CONFIG_ALT0);
 428                         mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
 429                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 430                                 PAD_CTL_SRE_FAST);
 431                         mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
 432                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 433                                 PAD_CTL_SRE_FAST);
 434                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
 435                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 436                                 PAD_CTL_SRE_FAST);
 437                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
 438                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 439                                 PAD_CTL_SRE_FAST);
 440                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
 441                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 442                                 PAD_CTL_SRE_FAST);
 443                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
 444                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 445                                 PAD_CTL_SRE_FAST);
 446                         mxc_request_iomux(MX51_PIN_SD2_CMD,
 447                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 448                         mxc_request_iomux(MX51_PIN_GPIO1_6,
 449                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 450                         mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
 451                                 PAD_CTL_HYS_ENABLE);
 452                         mxc_request_iomux(MX51_PIN_GPIO1_5,
 453                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 454                         mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
 455                                 PAD_CTL_HYS_ENABLE);
 456                         break;
 457                 default:
 458                         printf("Warning: you configured more ESDHC controller"
 459                                 "(%d) as supported by the board(2)\n",
 460                                 CONFIG_SYS_FSL_ESDHC_NUM);
 461                         return status;
 462                 }
 463                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 464         }
 465         return status;
 466 }
 467 #endif
 468
 469 int board_early_init_f(void)
 470 {
 471         setup_iomux_uart();
 472         setup_iomux_fec();
 473 #ifdef CONFIG_USB_EHCI_MX5
 474         setup_usb_h1();
 475 #endif
 476         setup_iomux_lcd();
 477
 478         return 0;
 479 }
 480
 481 int board_init(void)
 482 {
 483         /* address of boot parameters */
 484         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 485
 486         lcd_enable();
 487
 488         return 0;
 489 }
 490
 491 #ifdef CONFIG_BOARD_LATE_INIT
 492 int board_late_init(void)
 493 {
 494 #ifdef CONFIG_MXC_SPI
 495         setup_iomux_spi();
 496         power_init();
 497 #endif
 498
 499         return 0;
 500 }
 501 #endif
 502
 503 /*
 504  * Do not overwrite the console
 505  * Use always serial for U-Boot console
 506  */
 507 int overwrite_console(void)
 508 {
 509         return 1;
 510 }
 511
 512 int checkboard(void)
 513 {
 514         puts("Board: MX51EVK\n");
 515
 516         return 0;
 517 }