2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/iomux.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
34 #include <fsl_esdhc.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 static u32 system_rev;
43 #ifdef CONFIG_FSL_ESDHC
44 struct fsl_esdhc_cfg esdhc_cfg[2] = {
45 {MMC_SDHC1_BASE_ADDR, 1},
46 {MMC_SDHC2_BASE_ADDR, 1},
50 u32 get_board_rev(void)
57 /* dram_init must store complete ramsize in gd->ram_size */
58 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
63 static void setup_iomux_uart(void)
65 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
66 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
68 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
69 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
70 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
71 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
72 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
73 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
74 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
75 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
78 static void setup_iomux_fec(void)
81 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
82 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
85 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
86 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
89 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
90 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
93 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
94 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
97 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
98 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
101 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
102 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
105 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
106 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
109 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
110 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
113 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
114 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
117 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
118 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
121 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
122 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
125 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
126 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
129 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
130 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
133 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
134 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
137 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
138 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
141 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
142 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
145 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
146 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
149 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
150 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
153 #ifdef CONFIG_MXC_SPI
154 static void setup_iomux_spi(void)
156 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
157 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
158 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
160 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
161 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
162 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
164 /* de-select SS1 of instance: ecspi1. */
165 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
166 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
168 /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
169 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
170 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
172 /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
173 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
174 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
176 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
177 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
178 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
182 static void power_init(void)
185 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
191 /* Write needed to Power Gate 2 register */
192 pmic_reg_read(p, REG_POWER_MISC, &val);
194 pmic_reg_write(p, REG_POWER_MISC, val);
196 /* Externally powered */
197 pmic_reg_read(p, REG_CHARGE, &val);
198 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
199 pmic_reg_write(p, REG_CHARGE, val);
201 /* power up the system first */
202 pmic_reg_write(p, REG_POWER_MISC, PWUP);
204 /* Set core voltage to 1.1V */
205 pmic_reg_read(p, REG_SW_0, &val);
206 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
207 pmic_reg_write(p, REG_SW_0, val);
209 /* Setup VCC (SW2) to 1.25 */
210 pmic_reg_read(p, REG_SW_1, &val);
211 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
212 pmic_reg_write(p, REG_SW_1, val);
214 /* Setup 1V2_DIG1 (SW3) to 1.25 */
215 pmic_reg_read(p, REG_SW_2, &val);
216 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
217 pmic_reg_write(p, REG_SW_2, val);
220 /* Raise the core frequency to 800MHz */
221 writel(0x0, &mxc_ccm->cacrr);
223 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
224 /* Setup the switcher mode for SW1 & SW2*/
225 pmic_reg_read(p, REG_SW_4, &val);
226 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
227 (SWMODE_MASK << SWMODE2_SHIFT)));
228 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
229 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
230 pmic_reg_write(p, REG_SW_4, val);
232 /* Setup the switcher mode for SW3 & SW4 */
233 pmic_reg_read(p, REG_SW_5, &val);
234 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
235 (SWMODE_MASK << SWMODE4_SHIFT)));
236 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
237 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
238 pmic_reg_write(p, REG_SW_5, val);
240 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
241 pmic_reg_read(p, REG_SETTING_0, &val);
242 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
243 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
244 pmic_reg_write(p, REG_SETTING_0, val);
246 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
247 pmic_reg_read(p, REG_SETTING_1, &val);
248 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
249 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
250 pmic_reg_write(p, REG_SETTING_1, val);
252 /* Configure VGEN3 and VCAM regulators to use external PNP */
253 val = VGEN3CONFIG | VCAMCONFIG;
254 pmic_reg_write(p, REG_MODE_1, val);
257 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
258 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
259 VVIDEOEN | VAUDIOEN | VSDEN;
260 pmic_reg_write(p, REG_MODE_1, val);
262 mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
263 gpio_direction_output(46, 0);
267 gpio_set_value(46, 1);
270 #ifdef CONFIG_FSL_ESDHC
271 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
273 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
275 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
276 *cd = gpio_get_value(0);
278 *cd = gpio_get_value(6);
283 int board_mmc_init(bd_t *bis)
288 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
292 mxc_request_iomux(MX51_PIN_SD1_CMD,
293 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
294 mxc_request_iomux(MX51_PIN_SD1_CLK,
295 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
296 mxc_request_iomux(MX51_PIN_SD1_DATA0,
297 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
298 mxc_request_iomux(MX51_PIN_SD1_DATA1,
299 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
300 mxc_request_iomux(MX51_PIN_SD1_DATA2,
301 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
302 mxc_request_iomux(MX51_PIN_SD1_DATA3,
303 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
304 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
305 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
306 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
308 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
309 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
310 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
311 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
313 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
314 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
315 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
316 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
318 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
319 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
320 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
321 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
323 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
324 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
325 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
326 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
328 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
329 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
330 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
331 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
333 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
334 mxc_request_iomux(MX51_PIN_GPIO1_0,
335 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
336 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
338 mxc_request_iomux(MX51_PIN_GPIO1_1,
339 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
340 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
344 mxc_request_iomux(MX51_PIN_SD2_CMD,
345 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
346 mxc_request_iomux(MX51_PIN_SD2_CLK,
347 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
348 mxc_request_iomux(MX51_PIN_SD2_DATA0,
350 mxc_request_iomux(MX51_PIN_SD2_DATA1,
352 mxc_request_iomux(MX51_PIN_SD2_DATA2,
354 mxc_request_iomux(MX51_PIN_SD2_DATA3,
356 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
357 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
359 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
360 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
362 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
363 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
365 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
366 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
368 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
369 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
371 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
372 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
374 mxc_request_iomux(MX51_PIN_SD2_CMD,
375 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
376 mxc_request_iomux(MX51_PIN_GPIO1_6,
377 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
378 mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
380 mxc_request_iomux(MX51_PIN_GPIO1_5,
381 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
382 mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
386 printf("Warning: you configured more ESDHC controller"
387 "(%d) as supported by the board(2)\n",
388 CONFIG_SYS_FSL_ESDHC_NUM);
391 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
397 int board_early_init_f(void)
407 system_rev = get_cpu_rev();
409 /* address of boot parameters */
410 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
415 #ifdef CONFIG_BOARD_LATE_INIT
416 int board_late_init(void)
418 #ifdef CONFIG_MXC_SPI
428 puts("Board: MX51EVK\n");