2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/iomux-mx51.h>
28 #include <asm/errno.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
32 #include <asm/imx-common/mx5_video.h>
35 #include <fsl_esdhc.h>
36 #include <power/pmic.h>
39 #include <usb/ehci-fsl.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 #ifdef CONFIG_FSL_ESDHC
44 struct fsl_esdhc_cfg esdhc_cfg[2] = {
45 {MMC_SDHC1_BASE_ADDR},
46 {MMC_SDHC2_BASE_ADDR},
52 /* dram_init must store complete ramsize in gd->ram_size */
53 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
58 u32 get_board_rev(void)
60 u32 rev = get_cpu_rev();
61 if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
62 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
66 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
68 static void setup_iomux_uart(void)
70 static const iomux_v3_cfg_t uart_pads[] = {
71 MX51_PAD_UART1_RXD__UART1_RXD,
72 MX51_PAD_UART1_TXD__UART1_TXD,
73 NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
74 NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
77 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
80 static void setup_iomux_fec(void)
82 static const iomux_v3_cfg_t fec_pads[] = {
83 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
84 PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
85 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
86 MX51_PAD_NANDF_CS3__FEC_MDC,
87 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
88 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
89 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
90 MX51_PAD_NANDF_D9__FEC_RDATA0,
91 MX51_PAD_NANDF_CS6__FEC_TDATA3,
92 MX51_PAD_NANDF_CS5__FEC_TDATA2,
93 MX51_PAD_NANDF_CS4__FEC_TDATA1,
94 MX51_PAD_NANDF_D8__FEC_TDATA0,
95 MX51_PAD_NANDF_CS7__FEC_TX_EN,
96 MX51_PAD_NANDF_CS2__FEC_TX_ER,
97 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
98 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
99 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
100 MX51_PAD_EIM_CS5__FEC_CRS,
101 MX51_PAD_EIM_CS4__FEC_RX_ER,
102 NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
105 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
108 #ifdef CONFIG_MXC_SPI
109 static void setup_iomux_spi(void)
111 static const iomux_v3_cfg_t spi_pads[] = {
112 NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
113 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
114 NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
115 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
116 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
118 MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
119 NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
120 NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
121 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
124 imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
128 #ifdef CONFIG_USB_EHCI_MX5
129 #define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7)
130 #define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27)
131 #define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 2)
132 #define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5)
134 static void setup_usb_h1(void)
136 static const iomux_v3_cfg_t usb_h1_pads[] = {
137 MX51_PAD_USBH1_CLK__USBH1_CLK,
138 MX51_PAD_USBH1_DIR__USBH1_DIR,
139 MX51_PAD_USBH1_STP__USBH1_STP,
140 MX51_PAD_USBH1_NXT__USBH1_NXT,
141 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
142 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
143 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
144 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
145 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
146 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
147 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
148 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
150 NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
151 MX51_PAD_EIM_D17__GPIO2_1,
152 MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
155 imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
158 int board_ehci_hcd_init(int port)
160 /* Set USBH1_STP to GPIO and toggle it */
161 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
162 MX51_USBH_PAD_CTRL));
164 gpio_direction_output(MX51EVK_USBH1_STP, 0);
165 gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
167 gpio_set_value(MX51EVK_USBH1_STP, 1);
169 /* Set back USBH1_STP to be function */
170 imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
172 /* De-assert USB PHY RESETB */
173 gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
175 /* Drive USB_CLK_EN_B line low */
176 gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
179 gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
181 gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
186 static void power_init(void)
189 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
193 ret = pmic_init(I2C_PMIC);
197 p = pmic_get("FSL_PMIC");
201 /* Write needed to Power Gate 2 register */
202 pmic_reg_read(p, REG_POWER_MISC, &val);
204 pmic_reg_write(p, REG_POWER_MISC, val);
206 /* Externally powered */
207 pmic_reg_read(p, REG_CHARGE, &val);
208 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
209 pmic_reg_write(p, REG_CHARGE, val);
211 /* power up the system first */
212 pmic_reg_write(p, REG_POWER_MISC, PWUP);
214 /* Set core voltage to 1.1V */
215 pmic_reg_read(p, REG_SW_0, &val);
216 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
217 pmic_reg_write(p, REG_SW_0, val);
219 /* Setup VCC (SW2) to 1.25 */
220 pmic_reg_read(p, REG_SW_1, &val);
221 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
222 pmic_reg_write(p, REG_SW_1, val);
224 /* Setup 1V2_DIG1 (SW3) to 1.25 */
225 pmic_reg_read(p, REG_SW_2, &val);
226 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
227 pmic_reg_write(p, REG_SW_2, val);
230 /* Raise the core frequency to 800MHz */
231 writel(0x0, &mxc_ccm->cacrr);
233 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
234 /* Setup the switcher mode for SW1 & SW2*/
235 pmic_reg_read(p, REG_SW_4, &val);
236 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
237 (SWMODE_MASK << SWMODE2_SHIFT)));
238 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
239 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
240 pmic_reg_write(p, REG_SW_4, val);
242 /* Setup the switcher mode for SW3 & SW4 */
243 pmic_reg_read(p, REG_SW_5, &val);
244 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
245 (SWMODE_MASK << SWMODE4_SHIFT)));
246 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
247 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
248 pmic_reg_write(p, REG_SW_5, val);
250 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
251 pmic_reg_read(p, REG_SETTING_0, &val);
252 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
253 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
254 pmic_reg_write(p, REG_SETTING_0, val);
256 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
257 pmic_reg_read(p, REG_SETTING_1, &val);
258 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
259 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
260 pmic_reg_write(p, REG_SETTING_1, val);
262 /* Configure VGEN3 and VCAM regulators to use external PNP */
263 val = VGEN3CONFIG | VCAMCONFIG;
264 pmic_reg_write(p, REG_MODE_1, val);
267 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
268 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
269 VVIDEOEN | VAUDIOEN | VSDEN;
270 pmic_reg_write(p, REG_MODE_1, val);
272 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
274 gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
278 gpio_set_value(IMX_GPIO_NR(2, 14), 1);
281 #ifdef CONFIG_FSL_ESDHC
282 int board_mmc_getcd(struct mmc *mmc)
284 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
287 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
289 gpio_direction_input(IMX_GPIO_NR(1, 0));
290 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
292 gpio_direction_input(IMX_GPIO_NR(1, 6));
294 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
295 ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
297 ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
302 int board_mmc_init(bd_t *bis)
304 static const iomux_v3_cfg_t sd1_pads[] = {
305 NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
306 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
307 NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
308 PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
309 NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
310 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
311 NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
312 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
313 NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
314 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
315 NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
316 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
317 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
318 NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
321 static const iomux_v3_cfg_t sd2_pads[] = {
322 NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
323 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
324 NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
325 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
326 NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
327 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
328 NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
329 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
330 NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
331 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
332 NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
333 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
334 NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
335 NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
341 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
342 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
344 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
348 imx_iomux_v3_setup_multiple_pads(sd1_pads,
349 ARRAY_SIZE(sd1_pads));
352 imx_iomux_v3_setup_multiple_pads(sd2_pads,
353 ARRAY_SIZE(sd2_pads));
356 printf("Warning: you configured more ESDHC controller"
357 "(%d) as supported by the board(2)\n",
358 CONFIG_SYS_FSL_ESDHC_NUM);
361 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
367 int board_early_init_f(void)
371 #ifdef CONFIG_USB_EHCI_MX5
381 /* address of boot parameters */
382 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
387 #ifdef CONFIG_BOARD_LATE_INIT
388 int board_late_init(void)
390 #ifdef CONFIG_MXC_SPI
400 * Do not overwrite the console
401 * Use always serial for U-Boot console
403 int overwrite_console(void)
410 puts("Board: MX51EVK\n");