2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/errno.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/iomux-mx35.h>
17 #include <power/pmic.h>
20 #include <fsl_esdhc.h>
23 #include <linux/types.h>
25 #include <asm/arch/sys_proto.h>
27 #include <asm/mach-types.h>
29 #ifndef CONFIG_BOARD_LATE_INIT
30 #error "CONFIG_BOARD_LATE_INIT must be set for this board"
33 #ifndef CONFIG_BOARD_EARLY_INIT_F
34 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
37 DECLARE_GLOBAL_DATA_PTR;
43 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
44 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
46 gd->ram_size = size1 + size2;
51 int dram_init_banksize(void)
53 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
54 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
56 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
57 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
62 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
64 static void setup_iomux_i2c(void)
66 static const iomux_v3_cfg_t i2c1_pads[] = {
67 NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
68 NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
71 /* setup pins for I2C1 */
72 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
76 static void setup_iomux_spi(void)
78 static const iomux_v3_cfg_t spi_pads[] = {
79 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
80 MX35_PAD_CSPI1_MISO__CSPI1_MISO,
81 MX35_PAD_CSPI1_SS0__CSPI1_SS0,
82 MX35_PAD_CSPI1_SS1__CSPI1_SS1,
83 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
86 imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
89 #define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
90 PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
91 #define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
93 static void setup_iomux_usbotg(void)
95 static const iomux_v3_cfg_t usbotg_pads[] = {
96 NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
98 NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
102 /* Set up pins for USBOTG. */
103 imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
106 #define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
108 static void setup_iomux_fec(void)
110 static const iomux_v3_cfg_t fec_pads[] = {
111 NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
112 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
113 NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
114 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
115 NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
116 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
117 NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
118 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
119 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
120 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
121 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
122 NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
123 NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
124 NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
125 PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
126 NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
127 NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
128 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
129 NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
130 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
131 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
132 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
133 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
134 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
135 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
136 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
137 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
138 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
139 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
142 /* setup pins for FEC */
143 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
146 int board_early_init_f(void)
148 struct ccm_regs *ccm =
149 (struct ccm_regs *)IMX_CCM_BASE;
152 writel(readl(&ccm->cgr0) |
153 MXC_CCM_CGR0_EMI_MASK |
154 MXC_CCM_CGR0_EDIO_MASK |
155 MXC_CCM_CGR0_EPIT1_MASK,
158 writel(readl(&ccm->cgr1) |
159 MXC_CCM_CGR1_FEC_MASK |
160 MXC_CCM_CGR1_GPIO1_MASK |
161 MXC_CCM_CGR1_GPIO2_MASK |
162 MXC_CCM_CGR1_GPIO3_MASK |
163 MXC_CCM_CGR1_I2C1_MASK |
164 MXC_CCM_CGR1_I2C2_MASK |
165 MXC_CCM_CGR1_IPU_MASK,
169 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
172 setup_iomux_usbotg();
181 gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
182 /* address of boot parameters */
183 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
188 static inline int pmic_detect(void)
191 struct pmic *p = pmic_get("FSL_PMIC");
195 pmic_reg_read(p, REG_IDENTIFICATION, &id);
197 id = (id >> 6) & 0x7;
203 u32 get_board_rev(void)
209 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
212 int board_late_init(void)
219 ret = pmic_init(I2C_0);
224 p = pmic_get("FSL_PMIC");
225 imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
227 pmic_reg_read(p, REG_SETTING_0, &pmic_val);
228 pmic_reg_write(p, REG_SETTING_0,
229 pmic_val | VO_1_30V | VO_1_50V);
230 pmic_reg_read(p, REG_MODE_0, &pmic_val);
231 pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
233 imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
235 gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
238 val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
239 mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
242 val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
243 mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
247 mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
249 /* Print board revision */
250 printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
255 int board_eth_init(bd_t *bis)
257 #if defined(CONFIG_SMC911X)
258 int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
262 return cpu_eth_init(bis);
265 #if defined(CONFIG_FSL_ESDHC)
267 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
269 int board_mmc_init(bd_t *bis)
271 static const iomux_v3_cfg_t sdhc1_pads[] = {
272 MX35_PAD_SD1_CMD__ESDHC1_CMD,
273 MX35_PAD_SD1_CLK__ESDHC1_CLK,
274 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
275 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
276 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
277 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
280 /* configure pins for SDHC1 only */
281 imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
283 esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
284 return fsl_esdhc_initialize(bis, &esdhc_cfg);
287 int board_mmc_getcd(struct mmc *mmc)
289 return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);