2 * Copyright 2006, 2007 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
27 #include <asm/immap_fsl_pci.h>
28 #include <asm/fsl_ddr_sdram.h>
31 #include <fdt_support.h>
34 #include "../common/pixis.h"
36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
37 extern void ddr_enable_ecc(unsigned int dram_size);
40 long int fixed_sdram(void);
42 int board_early_init_f(void)
49 printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
50 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
51 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
52 in8(PIXIS_BASE + PIXIS_PVER));
58 initdram(int board_type)
62 #if defined(CONFIG_SPD_EEPROM)
63 dram_size = fsl_ddr_sdram();
65 dram_size = fixed_sdram();
68 #if defined(CFG_RAMBOOT)
73 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
75 * Initialize and enable DDR ECC.
77 ddr_enable_ecc(dram_size);
85 #if !defined(CONFIG_SPD_EEPROM)
87 * Fixed sdram init -- doesn't use serial presence detect.
92 #if !defined(CFG_RAMBOOT)
93 volatile immap_t *immap = (immap_t *) CFG_IMMR;
94 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
96 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
97 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
98 ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
99 ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
100 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
101 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
102 ddr->sdram_mode_1 = CFG_DDR_MODE_1;
103 ddr->sdram_mode_2 = CFG_DDR_MODE_2;
104 ddr->sdram_interval = CFG_DDR_INTERVAL;
105 ddr->sdram_data_init = CFG_DDR_DATA_INIT;
106 ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
107 ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
108 ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
110 #if defined (CONFIG_DDR_ECC)
111 ddr->err_disable = 0x0000008D;
112 ddr->err_sbe = 0x00ff0000;
118 #if defined (CONFIG_DDR_ECC)
119 /* Enable ECC checking */
120 ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
122 ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
123 ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
129 return CFG_SDRAM_SIZE * 1024 * 1024;
131 #endif /* !defined(CONFIG_SPD_EEPROM) */
134 #if defined(CONFIG_PCI)
136 * Initialize PCI Devices, report devices found.
139 #ifndef CONFIG_PCI_PNP
140 static struct pci_config_table pci_fsl86xxads_config_table[] = {
141 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
142 PCI_IDSEL_NUMBER, PCI_ANY_ID,
143 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
145 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
151 static struct pci_controller pci1_hose = {
152 #ifndef CONFIG_PCI_PNP
153 config_table:pci_mpc86xxcts_config_table
156 #endif /* CONFIG_PCI */
159 static struct pci_controller pci2_hose;
160 #endif /* CONFIG_PCI2 */
162 int first_free_busno = 0;
165 void pci_init_board(void)
167 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
168 volatile ccsr_gur_t *gur = &immap->im_gur;
169 uint devdisr = gur->devdisr;
170 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
171 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
175 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
176 extern void fsl_pci_init(struct pci_controller *hose);
177 struct pci_controller *hose = &pci1_hose;
179 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
180 >> MPC8641_PORBMSR_HA_SHIFT;
181 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
183 if ((io_sel == 2 || io_sel == 3 || io_sel == 5
184 || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
185 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
186 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
187 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
188 if (pci->pme_msg_det) {
189 pci->pme_msg_det = 0xffffffff;
190 debug(" with errors. Clearing. Now 0x%08x",
196 pci_set_region(hose->regions + 0,
200 PCI_REGION_MEM | PCI_REGION_MEMORY);
202 /* outbound memory */
203 pci_set_region(hose->regions + 1,
210 pci_set_region(hose->regions + 2,
216 hose->region_count = 3;
218 hose->first_busno=first_free_busno;
219 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
223 first_free_busno=hose->last_busno+1;
224 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
225 hose->first_busno,hose->last_busno);
228 * Activate ULI1575 legacy chip by performing a fake
229 * memory access. Needed to make ULI RTC work.
231 in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE
232 + CFG_PCI1_MEM_SIZE - 0x1000000)));
235 puts("PCI-EXPRESS 1: Disabled\n");
239 puts("PCI-EXPRESS1: Disabled\n");
240 #endif /* CONFIG_PCI1 */
244 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
245 extern void fsl_pci_init(struct pci_controller *hose);
246 struct pci_controller *hose = &pci2_hose;
250 pci_set_region(hose->regions + 0,
254 PCI_REGION_MEM | PCI_REGION_MEMORY);
256 /* outbound memory */
257 pci_set_region(hose->regions + 1,
264 pci_set_region(hose->regions + 2,
270 hose->region_count = 3;
272 hose->first_busno=first_free_busno;
273 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
277 first_free_busno=hose->last_busno+1;
278 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
279 hose->first_busno,hose->last_busno);
282 puts("PCI-EXPRESS 2: Disabled\n");
283 #endif /* CONFIG_PCI2 */
288 #if defined(CONFIG_OF_BOARD_SETUP)
291 ft_board_setup(void *blob, bd_t *bd)
296 ft_cpu_setup(blob, bd);
298 node = fdt_path_offset(blob, "/aliases");
302 path = fdt_getprop(blob, node, "pci0", NULL);
304 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
305 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
309 path = fdt_getprop(blob, node, "pci1", NULL);
311 tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
312 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
322 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
326 get_board_sys_clk(ulong dummy)
328 u8 i, go_bit, rd_clks;
331 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
334 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
338 * Only if both go bit and the SCLK bit in VCFGEN0 are set
339 * should we be using the AUX register. Remember, we also set the
340 * GO bit to boot from the alternate bank on the on-board flash
345 i = in8(PIXIS_BASE + PIXIS_AUX);
347 i = in8(PIXIS_BASE + PIXIS_SPD);
349 i = in8(PIXIS_BASE + PIXIS_SPD);
384 int board_eth_init(bd_t *bis)
386 /* Initialize TSECs */
388 return pci_eth_init(bis);