2 * Copyright 2006, 2007 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
27 #include <asm/immap_fsl_pci.h>
28 #include <asm/fsl_ddr_sdram.h>
31 #include <fdt_support.h>
34 #include "../common/pixis.h"
36 phys_size_t fixed_sdram(void);
38 int board_early_init_f(void)
45 printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
46 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
47 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
48 in8(PIXIS_BASE + PIXIS_PVER));
49 #ifdef CONFIG_PHYS_64BIT
50 printf (" 36-bit physical address map\n");
57 initdram(int board_type)
59 phys_size_t dram_size = 0;
61 #if defined(CONFIG_SPD_EEPROM)
62 dram_size = fsl_ddr_sdram();
64 dram_size = fixed_sdram();
67 #if defined(CONFIG_SYS_RAMBOOT)
77 #if !defined(CONFIG_SPD_EEPROM)
79 * Fixed sdram init -- doesn't use serial presence detect.
84 #if !defined(CONFIG_SYS_RAMBOOT)
85 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
86 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
88 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
89 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
90 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
91 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
92 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
93 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
94 ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
95 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
96 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
97 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
98 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
99 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
100 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
102 #if defined (CONFIG_DDR_ECC)
103 ddr->err_disable = 0x0000008D;
104 ddr->err_sbe = 0x00ff0000;
110 #if defined (CONFIG_DDR_ECC)
111 /* Enable ECC checking */
112 ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
114 ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
115 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
121 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
123 #endif /* !defined(CONFIG_SPD_EEPROM) */
126 #if defined(CONFIG_PCI)
127 static struct pci_controller pci1_hose;
128 #endif /* CONFIG_PCI */
131 static struct pci_controller pci2_hose;
132 #endif /* CONFIG_PCI2 */
134 int first_free_busno = 0;
136 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
137 extern void fsl_pci_init(struct pci_controller *hose);
139 void pci_init_board(void)
143 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
144 struct pci_controller *hose = &pci1_hose;
145 struct pci_region *r = hose->regions;
146 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
147 volatile ccsr_gur_t *gur = &immap->im_gur;
148 uint devdisr = gur->devdisr;
149 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
150 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
153 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
154 >> MPC8641_PORBMSR_HA_SHIFT;
155 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
157 if ((io_sel == 2 || io_sel == 3 || io_sel == 5
158 || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
159 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
160 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
161 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
162 if (pci->pme_msg_det) {
163 pci->pme_msg_det = 0xffffffff;
164 debug(" with errors. Clearing. Now 0x%08x",
169 /* outbound memory */
171 CONFIG_SYS_PCI1_MEM_BUS,
172 CONFIG_SYS_PCI1_MEM_PHYS,
173 CONFIG_SYS_PCI1_MEM_SIZE,
178 CONFIG_SYS_PCI1_IO_BUS,
179 CONFIG_SYS_PCI1_IO_PHYS,
180 CONFIG_SYS_PCI1_IO_SIZE,
184 r += fsl_pci_setup_inbound_windows(r);
186 hose->region_count = r - hose->regions;
188 hose->first_busno=first_free_busno;
189 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
193 first_free_busno=hose->last_busno+1;
194 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
195 hose->first_busno,hose->last_busno);
198 * Activate ULI1575 legacy chip by performing a fake
199 * memory access. Needed to make ULI RTC work.
201 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
202 + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
205 puts("PCI-EXPRESS 1: Disabled\n");
209 puts("PCI-EXPRESS1: Disabled\n");
210 #endif /* CONFIG_PCI1 */
214 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
215 struct pci_controller *hose = &pci2_hose;
216 struct pci_region *r = hose->regions;
218 /* outbound memory */
220 CONFIG_SYS_PCI2_MEM_BUS,
221 CONFIG_SYS_PCI2_MEM_PHYS,
222 CONFIG_SYS_PCI2_MEM_SIZE,
227 CONFIG_SYS_PCI2_IO_BUS,
228 CONFIG_SYS_PCI2_IO_PHYS,
229 CONFIG_SYS_PCI2_IO_SIZE,
233 r += fsl_pci_setup_inbound_windows(r);
235 hose->region_count = r - hose->regions;
237 hose->first_busno=first_free_busno;
238 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
242 first_free_busno=hose->last_busno+1;
243 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
244 hose->first_busno,hose->last_busno);
247 puts("PCI-EXPRESS 2: Disabled\n");
248 #endif /* CONFIG_PCI2 */
253 #if defined(CONFIG_OF_BOARD_SETUP)
254 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
255 struct pci_controller *hose);
258 ft_board_setup(void *blob, bd_t *bd)
264 ft_cpu_setup(blob, bd);
267 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
270 ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
274 * Warn if it looks like the device tree doesn't match u-boot.
275 * This is just an estimation, based on the location of CCSR,
276 * which is defined by the "reg" property in the soc node.
278 off = fdt_path_offset(blob, "/soc8641");
279 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
280 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
284 if (addrcells && (*addrcells == 1))
289 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
290 printf("WARNING: The CCSRBAR address in your .dts "
291 "does not match the address of the CCSR "
292 "in u-boot. This means your .dts might "
301 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
305 get_board_sys_clk(ulong dummy)
307 u8 i, go_bit, rd_clks;
310 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
313 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
317 * Only if both go bit and the SCLK bit in VCFGEN0 are set
318 * should we be using the AUX register. Remember, we also set the
319 * GO bit to boot from the alternate bank on the on-board flash
324 i = in8(PIXIS_BASE + PIXIS_AUX);
326 i = in8(PIXIS_BASE + PIXIS_SPD);
328 i = in8(PIXIS_BASE + PIXIS_SPD);
363 int board_eth_init(bd_t *bis)
365 /* Initialize TSECs */
367 return pci_eth_init(bis);
370 void board_reset(void)
372 out8(PIXIS_BASE + PIXIS_RST, 0);
378 #if (CONFIG_NUM_CPUS > 1)
379 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
381 void board_lmb_reserve(struct lmb *lmb)
383 cpu_mp_lmb_reserve(lmb);