2 * Copyright 2006, 2007 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
27 #include <asm/fsl_pci.h>
28 #include <asm/fsl_ddr_sdram.h>
31 #include <fdt_support.h>
34 #include "../common/pixis.h"
36 phys_size_t fixed_sdram(void);
38 int board_early_init_f(void)
46 u8 *pixis_base = (u8 *)PIXIS_BASE;
48 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
49 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
50 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
51 in_8(pixis_base + PIXIS_PVER));
53 vboot = in_8(pixis_base + PIXIS_VBOOT);
54 if (vboot & PIXIS_VBOOT_FMAP)
55 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
59 #ifdef CONFIG_PHYS_64BIT
60 printf (" 36-bit physical address map\n");
67 initdram(int board_type)
69 phys_size_t dram_size = 0;
71 #if defined(CONFIG_SPD_EEPROM)
72 dram_size = fsl_ddr_sdram();
74 dram_size = fixed_sdram();
77 #if defined(CONFIG_SYS_RAMBOOT)
87 #if !defined(CONFIG_SPD_EEPROM)
89 * Fixed sdram init -- doesn't use serial presence detect.
94 #if !defined(CONFIG_SYS_RAMBOOT)
95 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
96 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
98 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
99 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
100 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
101 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
102 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
103 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
104 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
105 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
106 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
107 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
108 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
109 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
110 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
112 #if defined (CONFIG_DDR_ECC)
113 ddr->err_disable = 0x0000008D;
114 ddr->err_sbe = 0x00ff0000;
120 #if defined (CONFIG_DDR_ECC)
121 /* Enable ECC checking */
122 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
124 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
125 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
131 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
133 #endif /* !defined(CONFIG_SPD_EEPROM) */
136 #if defined(CONFIG_PCI)
137 static struct pci_controller pci1_hose;
138 #endif /* CONFIG_PCI */
141 static struct pci_controller pci2_hose;
142 #endif /* CONFIG_PCI2 */
144 int first_free_busno = 0;
146 void pci_init_board(void)
150 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
151 struct pci_controller *hose = &pci1_hose;
152 struct pci_region *r = hose->regions;
153 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
154 volatile ccsr_gur_t *gur = &immap->im_gur;
155 uint devdisr = gur->devdisr;
156 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
157 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
158 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
161 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
162 >> MPC8641_PORBMSR_HA_SHIFT;
163 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
165 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
166 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
167 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
168 if (pci->pme_msg_det) {
169 pci->pme_msg_det = 0xffffffff;
170 debug(" with errors. Clearing. Now 0x%08x",
175 /* outbound memory */
177 CONFIG_SYS_PCI1_MEM_BUS,
178 CONFIG_SYS_PCI1_MEM_PHYS,
179 CONFIG_SYS_PCI1_MEM_SIZE,
184 CONFIG_SYS_PCI1_IO_BUS,
185 CONFIG_SYS_PCI1_IO_PHYS,
186 CONFIG_SYS_PCI1_IO_SIZE,
189 hose->region_count = r - hose->regions;
191 hose->first_busno=first_free_busno;
193 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
195 first_free_busno=hose->last_busno+1;
196 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
197 hose->first_busno,hose->last_busno);
200 * Activate ULI1575 legacy chip by performing a fake
201 * memory access. Needed to make ULI RTC work.
203 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
204 + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
207 puts("PCI-EXPRESS 1: Disabled\n");
211 puts("PCI-EXPRESS1: Disabled\n");
212 #endif /* CONFIG_PCI1 */
216 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
217 struct pci_controller *hose = &pci2_hose;
218 struct pci_region *r = hose->regions;
220 /* outbound memory */
222 CONFIG_SYS_PCI2_MEM_BUS,
223 CONFIG_SYS_PCI2_MEM_PHYS,
224 CONFIG_SYS_PCI2_MEM_SIZE,
229 CONFIG_SYS_PCI2_IO_BUS,
230 CONFIG_SYS_PCI2_IO_PHYS,
231 CONFIG_SYS_PCI2_IO_SIZE,
234 hose->region_count = r - hose->regions;
236 hose->first_busno=first_free_busno;
238 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
240 first_free_busno=hose->last_busno+1;
241 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
242 hose->first_busno,hose->last_busno);
245 puts("PCI-EXPRESS 2: Disabled\n");
246 #endif /* CONFIG_PCI2 */
251 #if defined(CONFIG_OF_BOARD_SETUP)
253 ft_board_setup(void *blob, bd_t *bd)
259 ft_cpu_setup(blob, bd);
262 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
265 ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
269 * Warn if it looks like the device tree doesn't match u-boot.
270 * This is just an estimation, based on the location of CCSR,
271 * which is defined by the "reg" property in the soc node.
273 off = fdt_path_offset(blob, "/soc8641");
274 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
275 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
279 if (addrcells && (*addrcells == 1))
284 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
285 printf("WARNING: The CCSRBAR address in your .dts "
286 "does not match the address of the CCSR "
287 "in u-boot. This means your .dts might "
296 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
300 get_board_sys_clk(ulong dummy)
302 u8 i, go_bit, rd_clks;
304 u8 *pixis_base = (u8 *)PIXIS_BASE;
306 go_bit = in_8(pixis_base + PIXIS_VCTL);
309 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
313 * Only if both go bit and the SCLK bit in VCFGEN0 are set
314 * should we be using the AUX register. Remember, we also set the
315 * GO bit to boot from the alternate bank on the on-board flash
320 i = in_8(pixis_base + PIXIS_AUX);
322 i = in_8(pixis_base + PIXIS_SPD);
324 i = in_8(pixis_base + PIXIS_SPD);
359 int board_eth_init(bd_t *bis)
361 /* Initialize TSECs */
363 return pci_eth_init(bis);
366 void board_reset(void)
368 u8 *pixis_base = (u8 *)PIXIS_BASE;
370 out_8(pixis_base + PIXIS_RST, 0);
377 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
379 void board_lmb_reserve(struct lmb *lmb)
381 cpu_mp_lmb_reserve(lmb);