2 * Copyright 2006, 2007, 2010 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
27 #include <asm/fsl_pci.h>
28 #include <asm/fsl_ddr_sdram.h>
29 #include <asm/fsl_serdes.h>
32 #include <fdt_support.h>
35 phys_size_t fixed_sdram(void);
37 int board_early_init_f(void)
45 u8 *pixis_base = (u8 *)PIXIS_BASE;
47 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
48 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
49 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
50 in_8(pixis_base + PIXIS_PVER));
52 vboot = in_8(pixis_base + PIXIS_VBOOT);
53 if (vboot & PIXIS_VBOOT_FMAP)
54 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
58 #ifdef CONFIG_PHYS_64BIT
59 printf (" 36-bit physical address map\n");
65 initdram(int board_type)
67 phys_size_t dram_size = 0;
69 #if defined(CONFIG_SPD_EEPROM)
70 dram_size = fsl_ddr_sdram();
72 dram_size = fixed_sdram();
75 setup_ddr_bat(dram_size);
82 #if !defined(CONFIG_SPD_EEPROM)
84 * Fixed sdram init -- doesn't use serial presence detect.
89 #if !defined(CONFIG_SYS_RAMBOOT)
90 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
91 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
93 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
94 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
95 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
96 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
97 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
98 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
99 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
100 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
101 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
102 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
103 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
104 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
105 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
107 #if defined (CONFIG_DDR_ECC)
108 ddr->err_disable = 0x0000008D;
109 ddr->err_sbe = 0x00ff0000;
115 #if defined (CONFIG_DDR_ECC)
116 /* Enable ECC checking */
117 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
119 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
120 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
126 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
128 #endif /* !defined(CONFIG_SPD_EEPROM) */
130 void pci_init_board(void)
132 fsl_pcie_init_board(0);
136 * Activate ULI1575 legacy chip by performing a fake
137 * memory access. Needed to make ULI RTC work.
139 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
140 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
141 #endif /* CONFIG_PCIE1 */
145 #if defined(CONFIG_OF_BOARD_SETUP)
147 ft_board_setup(void *blob, bd_t *bd)
153 ft_cpu_setup(blob, bd);
158 * Warn if it looks like the device tree doesn't match u-boot.
159 * This is just an estimation, based on the location of CCSR,
160 * which is defined by the "reg" property in the soc node.
162 off = fdt_path_offset(blob, "/soc8641");
163 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
164 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
168 if (addrcells && (*addrcells == 1))
173 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
174 printf("WARNING: The CCSRBAR address in your .dts "
175 "does not match the address of the CCSR "
176 "in u-boot. This means your .dts might "
185 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
189 get_board_sys_clk(ulong dummy)
191 u8 i, go_bit, rd_clks;
193 u8 *pixis_base = (u8 *)PIXIS_BASE;
195 go_bit = in_8(pixis_base + PIXIS_VCTL);
198 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
202 * Only if both go bit and the SCLK bit in VCFGEN0 are set
203 * should we be using the AUX register. Remember, we also set the
204 * GO bit to boot from the alternate bank on the on-board flash
209 i = in_8(pixis_base + PIXIS_AUX);
211 i = in_8(pixis_base + PIXIS_SPD);
213 i = in_8(pixis_base + PIXIS_SPD);
248 int board_eth_init(bd_t *bis)
250 /* Initialize TSECs */
252 return pci_eth_init(bis);
255 void board_reset(void)
257 u8 *pixis_base = (u8 *)PIXIS_BASE;
259 out_8(pixis_base + PIXIS_RST, 0);
266 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
268 void board_lmb_reserve(struct lmb *lmb)
270 cpu_mp_lmb_reserve(lmb);