2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
33 #include <asm/fsl_serdes.h>
36 #include <fdt_support.h>
40 #include "../common/sgmii_riser.h"
42 long int fixed_sdram(void);
47 u8 *pixis_base = (u8 *)PIXIS_BASE;
49 puts ("Board: MPC8572DS ");
50 #ifdef CONFIG_PHYS_64BIT
51 puts ("(36-bit addrmap) ");
53 printf ("Sys ID: 0x%02x, "
54 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
55 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
56 in_8(pixis_base + PIXIS_PVER));
58 vboot = in_8(pixis_base + PIXIS_VBOOT);
59 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
60 case PIXIS_VBOOT_LBMAP_NOR0:
63 case PIXIS_VBOOT_LBMAP_PJET:
66 case PIXIS_VBOOT_LBMAP_NAND:
69 case PIXIS_VBOOT_LBMAP_NOR1:
77 phys_size_t initdram(int board_type)
79 phys_size_t dram_size = 0;
81 puts("Initializing....");
83 #ifdef CONFIG_SPD_EEPROM
84 dram_size = fsl_ddr_sdram();
86 dram_size = fixed_sdram();
88 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
89 dram_size *= 0x100000;
95 #if !defined(CONFIG_SPD_EEPROM)
97 * Fixed sdram init -- doesn't use serial presence detect.
100 phys_size_t fixed_sdram (void)
102 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
103 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
106 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
107 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
109 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
110 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
111 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
112 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
113 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
114 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
115 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
116 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
117 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
118 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
120 #if defined (CONFIG_DDR_ECC)
121 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
122 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
123 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
129 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
131 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
133 debug("DDR - 1st controller: memory initializing\n");
135 * Poll until memory is initialized.
136 * 512 Meg at 400 might hit this 200 times or so.
138 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
141 debug("DDR: memory initialized\n\n");
146 return 512 * 1024 * 1024;
152 static struct pci_controller pcie1_hose;
156 static struct pci_controller pcie2_hose;
160 static struct pci_controller pcie3_hose;
164 void pci_init_board(void)
166 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
167 struct fsl_pci_info pci_info[3];
168 u32 devdisr, pordevsr, io_sel, temp32;
169 int first_free_busno = 0;
172 int pcie_ep, pcie_configured;
174 devdisr = in_be32(&gur->devdisr);
175 pordevsr = in_be32(&gur->pordevsr);
176 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
178 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
180 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
181 printf("eTSEC1 is in sgmii mode.\n");
182 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
183 printf("eTSEC2 is in sgmii mode.\n");
184 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
185 printf("eTSEC3 is in sgmii mode.\n");
186 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
187 printf("eTSEC4 is in sgmii mode.\n");
191 pcie_configured = is_serdes_configured(PCIE3);
193 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
194 SET_STD_PCIE_INFO(pci_info[num], 3);
195 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
196 printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
197 pcie_ep ? "Endpoint" : "Root Complex",
199 first_free_busno = fsl_pci_init_port(&pci_info[num++],
200 &pcie3_hose, first_free_busno);
202 * Activate ULI1575 legacy chip by performing a fake
203 * memory access. Needed to make ULI RTC work.
204 * Device 1d has the first on-board memory BAR.
206 pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0),
207 PCI_BASE_ADDRESS_1, &temp32);
208 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
209 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
211 debug(" uli1572 read to %p\n", p);
215 printf("PCIE3: disabled\n");
219 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
223 pcie_configured = is_serdes_configured(PCIE2);
225 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
226 SET_STD_PCIE_INFO(pci_info[num], 2);
227 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
228 printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
229 pcie_ep ? "Endpoint" : "Root Complex",
231 first_free_busno = fsl_pci_init_port(&pci_info[num++],
232 &pcie2_hose, first_free_busno);
234 printf("PCIE2: disabled\n");
239 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
243 pcie_configured = is_serdes_configured(PCIE1);
245 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
246 SET_STD_PCIE_INFO(pci_info[num], 1);
247 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
248 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
249 pcie_ep ? "Endpoint" : "Root Complex",
251 first_free_busno = fsl_pci_init_port(&pci_info[num++],
252 &pcie1_hose, first_free_busno);
254 printf("PCIE1: disabled\n");
259 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
264 int board_early_init_r(void)
266 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
267 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
270 * Remap Boot flash + PROMJET region to caching-inhibited
271 * so that flash can be erased properly.
274 /* Flush d-cache and invalidate i-cache of any FLASH data */
278 /* invalidate existing TLB entry for flash + promjet */
279 disable_tlb(flash_esel);
281 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
282 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
283 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
288 #ifdef CONFIG_TSEC_ENET
289 int board_eth_init(bd_t *bis)
291 struct tsec_info_struct tsec_info[4];
292 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
296 SET_STD_TSEC_INFO(tsec_info[num], 1);
297 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
298 tsec_info[num].flags |= TSEC_SGMII;
302 SET_STD_TSEC_INFO(tsec_info[num], 2);
303 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
304 tsec_info[num].flags |= TSEC_SGMII;
308 SET_STD_TSEC_INFO(tsec_info[num], 3);
309 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
310 tsec_info[num].flags |= TSEC_SGMII;
314 SET_STD_TSEC_INFO(tsec_info[num], 4);
315 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
316 tsec_info[num].flags |= TSEC_SGMII;
321 printf("No TSECs initialized\n");
326 #ifdef CONFIG_FSL_SGMII_RISER
327 fsl_sgmii_riser_init(tsec_info, num);
330 tsec_eth_init(bis, tsec_info, num);
332 return pci_eth_init(bis);
336 #if defined(CONFIG_OF_BOARD_SETUP)
337 void ft_board_setup(void *blob, bd_t *bd)
342 ft_cpu_setup(blob, bd);
344 base = getenv_bootm_low();
345 size = getenv_bootm_size();
347 fdt_fixup_memory(blob, (u64)base, (u64)size);
351 #ifdef CONFIG_FSL_SGMII_RISER
352 fsl_sgmii_riser_fdt_fixup(blob);
358 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
360 void board_lmb_reserve(struct lmb *lmb)
362 cpu_mp_lmb_reserve(lmb);