2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
14 struct board_specific_parameters {
16 u32 datarate_mhz_high;
24 * This table contains all valid speeds we want to override with board
25 * specific parameters. datarate_mhz_high values need to be in ascending order
26 * for each n_ranks group.
28 * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
29 * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
30 * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
31 * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
32 * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
34 * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
36 static const struct board_specific_parameters udimm0[] = {
39 * num| hi| clk| cpo|wrdata|2T
40 * ranks| mhz|adjst| | delay|
44 {2, 549, 8, 11, 5, 0},
45 {2, 680, 8, 10, 5, 0},
46 {2, 850, 8, 12, 5, 1},
49 {1, 549, 6, 11, 3, 0},
50 {1, 680, 1, 10, 5, 0},
51 {1, 850, 1, 12, 5, 0},
55 static const struct board_specific_parameters udimm1[] = {
58 * num| hi| clk| cpo|wrdata|2T
59 * ranks| mhz|adjst| | delay|
63 {2, 549, 8, 11, 5, 0},
64 {2, 680, 8, 11, 5, 0},
65 {2, 850, 8, 13, 5, 1},
68 {1, 549, 6, 11, 3, 0},
69 {1, 680, 1, 11, 6, 0},
70 {1, 850, 1, 13, 6, 0},
74 static const struct board_specific_parameters *udimms[] = {
79 static const struct board_specific_parameters rdimm0[] = {
82 * num| hi| clk| cpo|wrdata|2T
83 * ranks| mhz|adjst| | delay|
87 {2, 549, 4, 11, 3, 0},
88 {2, 680, 4, 10, 3, 0},
89 {2, 850, 4, 12, 3, 1},
93 static const struct board_specific_parameters rdimm1[] = {
96 * num| hi| clk| cpo|wrdata|2T
97 * ranks| mhz|adjst| | delay|
100 {2, 400, 4, 9, 3, 0},
101 {2, 549, 4, 11, 3, 0},
102 {2, 680, 4, 11, 3, 0},
103 {2, 850, 4, 13, 3, 1},
107 static const struct board_specific_parameters *rdimms[] = {
112 void fsl_ddr_board_options(memctl_options_t *popts,
113 dimm_params_t *pdimm,
114 unsigned int ctrl_num)
116 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
120 printf("Wrong parameter for controller number %d", ctrl_num);
126 if (popts->registered_dimm_en)
127 pbsp = rdimms[ctrl_num];
129 pbsp = udimms[ctrl_num];
131 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
132 * freqency and n_banks specified in board_specific_parameters table.
134 ddr_freq = get_ddr_freq(0) / 1000000;
135 while (pbsp->datarate_mhz_high) {
136 if (pbsp->n_ranks == pdimm->n_ranks) {
137 if (ddr_freq <= pbsp->datarate_mhz_high) {
138 popts->clk_adjust = pbsp->clk_adjust;
139 popts->cpo_override = pbsp->cpo;
140 popts->write_data_delay =
141 pbsp->write_data_delay;
142 popts->twot_en = pbsp->force_2t;
151 printf("Error: board specific timing not found "
152 "for data rate %lu MT/s!\n"
153 "Trying to use the highest speed (%u) parameters\n",
154 ddr_freq, pbsp_highest->datarate_mhz_high);
155 popts->clk_adjust = pbsp->clk_adjust;
156 popts->cpo_override = pbsp->cpo;
157 popts->write_data_delay = pbsp->write_data_delay;
158 popts->twot_en = pbsp->force_2t;
160 panic("DIMM is not supported by this board");
165 * Factors to consider for half-strength driver enable:
166 * - number of DIMMs installed
168 popts->half_strength_driver_enable = 0;