2 * Copyright 2004, 2007 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/immap_fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <spd_sdram.h>
35 #include <fdt_support.h>
37 #include "../common/cadmus.h"
38 #include "../common/eeprom.h"
39 #include "../common/via.h"
41 DECLARE_GLOBAL_DATA_PTR;
43 void local_bus_init(void);
44 void sdram_init(void);
48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
51 /* PCI slot in USER bits CSR[6:7] by convention. */
52 uint pci_slot = get_pci_slot ();
54 uint cpu_board_rev = get_cpu_board_revision ();
56 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
57 get_board_version (), pci_slot);
59 printf ("CPU Board Revision %d.%d (0x%04x)\n",
60 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
61 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
63 * Initialize local bus.
68 * Hack TSEC 3 and 4 IO voltages.
70 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
72 ecm->eedr = 0xffffffff; /* clear ecm errors */
73 ecm->eeer = 0xffffffff; /* enable ecm errors */
78 initdram(int board_type)
82 puts("Initializing\n");
84 #if defined(CONFIG_DDR_DLL)
87 * Work around to stabilize DDR DLL MSYNC_IN.
88 * Errata DDR9 seems to have been fixed.
89 * This is now the workaround for Errata DDR11:
90 * Override DLL = 1, Course Adj = 1, Tap Select = 0
93 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
95 gur->ddrdllcr = 0x81000000;
96 asm("sync;isync;msync");
101 dram_size = fsl_ddr_sdram();
102 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
103 dram_size *= 0x100000;
106 * SDRAM Initialization
115 * Initialize Local Bus
120 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
121 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
127 get_sys_info(&sysinfo);
128 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
129 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
131 gur->lbiuiplldcr1 = 0x00078080;
133 gur->lbiuiplldcr0 = 0x7c0f1bf0;
134 } else if (clkdiv == 8) {
135 gur->lbiuiplldcr0 = 0x6c0f1bf0;
136 } else if (clkdiv == 4) {
137 gur->lbiuiplldcr0 = 0x5c0f1bf0;
140 lbc->lcrr |= 0x00030000;
142 asm("sync;isync;msync");
144 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
145 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
149 * Initialize SDRAM memory on the Local Bus.
154 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
157 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
158 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
164 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
167 * Setup SDRAM Base and Option Registers
169 lbc->or2 = CONFIG_SYS_OR2_PRELIM;
172 lbc->br2 = CONFIG_SYS_BR2_PRELIM;
175 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
179 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
180 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
184 * MPC8548 uses "new" 15-16 style addressing.
186 cpu_board_rev = get_cpu_board_revision();
187 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
188 lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
191 * Issue PRECHARGE ALL command.
193 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
196 ppcDcbf((unsigned long) sdram_addr);
200 * Issue 8 AUTO REFRESH commands.
202 for (idx = 0; idx < 8; idx++) {
203 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
206 ppcDcbf((unsigned long) sdram_addr);
211 * Issue 8 MODE-set command.
213 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
216 ppcDcbf((unsigned long) sdram_addr);
220 * Issue NORMAL OP command.
222 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
225 ppcDcbf((unsigned long) sdram_addr);
226 udelay(200); /* Overkill. Must wait > 200 bus cycles */
228 #endif /* enable SDRAM init */
231 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
232 /* For some reason the Tundra PCI bridge shows up on itself as a
233 * different device. Work around that by refusing to configure it.
235 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
237 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
238 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
239 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
240 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
241 mpc85xx_config_via_usbide, {0,0,0}},
242 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
243 mpc85xx_config_via_usb, {0,0,0}},
244 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
245 mpc85xx_config_via_usb2, {0,0,0}},
246 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
247 mpc85xx_config_via_power, {0,0,0}},
248 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
249 mpc85xx_config_via_ac97, {0,0,0}},
253 static struct pci_controller pci1_hose = {
254 config_table: pci_mpc85xxcds_config_table};
255 #endif /* CONFIG_PCI */
258 static struct pci_controller pci2_hose;
259 #endif /* CONFIG_PCI2 */
262 static struct pci_controller pcie1_hose;
263 #endif /* CONFIG_PCIE1 */
265 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
266 extern void fsl_pci_init(struct pci_controller *hose);
268 int first_free_busno=0;
273 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
274 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
275 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
280 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
281 struct pci_controller *hose = &pci1_hose;
282 struct pci_config_table *table;
283 struct pci_region *r = hose->regions;
285 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
286 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
287 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
289 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
291 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
293 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
294 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
296 (pci_speed == 33333000) ? "33" :
297 (pci_speed == 66666000) ? "66" : "unknown",
298 pci_clk_sel ? "sync" : "async",
299 pci_agent ? "agent" : "host",
300 pci_arb ? "arbiter" : "external-arbiter"
305 r += fsl_pci_setup_inbound_windows(r);
307 /* outbound memory */
309 CONFIG_SYS_PCI1_MEM_BUS,
310 CONFIG_SYS_PCI1_MEM_PHYS,
311 CONFIG_SYS_PCI1_MEM_SIZE,
316 CONFIG_SYS_PCI1_IO_BUS,
317 CONFIG_SYS_PCI1_IO_PHYS,
318 CONFIG_SYS_PCI1_IO_SIZE,
320 hose->region_count = r - hose->regions;
322 /* relocate config table pointers */
323 hose->config_table = \
324 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
325 for (table = hose->config_table; table && table->vendor; table++)
326 table->config_device += gd->reloc_off;
328 hose->first_busno=first_free_busno;
329 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
332 first_free_busno=hose->last_busno+1;
333 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
334 #ifdef CONFIG_PCIX_CHECK
335 if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
337 if (CONFIG_SYS_CLK_FREQ < 66000000)
338 printf("PCI-X will only work at 66 MHz\n");
340 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
341 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
342 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
346 printf (" PCI: disabled\n");
350 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
355 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
356 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
358 printf (" PCI2: 32 bit, 66 MHz, %s\n",
359 pci2_clk_sel ? "sync" : "async");
361 printf (" PCI2: disabled\n");
365 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
366 #endif /* CONFIG_PCI2 */
370 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
371 struct pci_controller *hose = &pcie1_hose;
372 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
373 struct pci_region *r = hose->regions;
375 int pcie_configured = io_sel >= 1;
377 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
378 printf ("\n PCIE connected to slot as %s (base address %x)",
379 pcie_ep ? "End Point" : "Root Complex",
382 if (pci->pme_msg_det) {
383 pci->pme_msg_det = 0xffffffff;
384 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
389 r += fsl_pci_setup_inbound_windows(r);
391 /* outbound memory */
393 CONFIG_SYS_PCIE1_MEM_BUS,
394 CONFIG_SYS_PCIE1_MEM_PHYS,
395 CONFIG_SYS_PCIE1_MEM_SIZE,
400 CONFIG_SYS_PCIE1_IO_BUS,
401 CONFIG_SYS_PCIE1_IO_PHYS,
402 CONFIG_SYS_PCIE1_IO_SIZE,
405 hose->region_count = r - hose->regions;
407 hose->first_busno=first_free_busno;
408 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
411 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
413 first_free_busno=hose->last_busno+1;
416 printf (" PCIE: disabled\n");
420 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
425 int last_stage_init(void)
429 /* Change the resistors for the PHY */
430 /* This is needed to get the RGMII working for the 1.3+
432 if (get_board_version() == 0x13) {
433 miiphy_write(CONFIG_TSEC1_NAME,
434 TSEC1_PHY_ADDR, 29, 18);
436 miiphy_read(CONFIG_TSEC1_NAME,
437 TSEC1_PHY_ADDR, 30, &temp);
439 temp = (temp & 0xf03f);
440 temp |= 2 << 9; /* 36 ohm */
441 temp |= 2 << 6; /* 39 ohm */
443 miiphy_write(CONFIG_TSEC1_NAME,
444 TSEC1_PHY_ADDR, 30, temp);
446 miiphy_write(CONFIG_TSEC1_NAME,
447 TSEC1_PHY_ADDR, 29, 3);
449 miiphy_write(CONFIG_TSEC1_NAME,
450 TSEC1_PHY_ADDR, 30, 0x8000);
457 #if defined(CONFIG_OF_BOARD_SETUP)
458 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
459 struct pci_controller *hose);
461 void ft_pci_setup(void *blob, bd_t *bd)
464 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
467 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);