1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
9 #include <display_options.h>
14 #include <asm/processor.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_pci.h>
18 #include <fsl_ddr_sdram.h>
19 #include <asm/fsl_serdes.h>
21 #include <linux/delay.h>
22 #include <linux/libfdt.h>
23 #include <fdt_support.h>
28 #include "../common/cadmus.h"
29 #include "../common/eeprom.h"
30 #include "../common/via.h"
32 void local_bus_init(void);
36 volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
37 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
39 /* PCI slot in USER bits CSR[6:7] by convention. */
40 uint pci_slot = get_pci_slot ();
42 uint cpu_board_rev = get_cpu_board_revision ();
44 puts("Board: MPC8548CDS");
45 printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
46 get_board_version(), pci_slot);
47 printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
48 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
49 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
51 * Initialize local bus.
56 * Hack TSEC 3 and 4 IO voltages.
58 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
60 ecm->eedr = 0xffffffff; /* clear ecm errors */
61 ecm->eeer = 0xffffffff; /* enable ecm errors */
66 * Initialize Local Bus
71 volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
72 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
77 get_sys_info(&sysinfo);
78 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
80 gur->lbiuiplldcr1 = 0x00078080;
82 gur->lbiuiplldcr0 = 0x7c0f1bf0;
83 } else if (clkdiv == 8) {
84 gur->lbiuiplldcr0 = 0x6c0f1bf0;
85 } else if (clkdiv == 4) {
86 gur->lbiuiplldcr0 = 0x5c0f1bf0;
89 lbc->lcrr |= 0x00030000;
91 asm("sync;isync;msync");
93 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
94 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
98 * Initialize SDRAM memory on the Local Bus.
100 void lbc_sdram_init(void)
102 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
105 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
106 uint *sdram_addr = (uint *)CFG_SYS_LBC_SDRAM_BASE;
110 print_size(CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
114 * Setup SDRAM Base and Option Registers
116 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
117 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
118 lbc->lbcr = CFG_SYS_LBC_LBCR;
121 lbc->lsrt = CFG_SYS_LBC_LSRT;
122 lbc->mrtpr = CFG_SYS_LBC_MRTPR;
126 * MPC8548 uses "new" 15-16 style addressing.
128 lsdmr_common = CFG_SYS_LBC_LSDMR_COMMON;
129 lsdmr_common |= LSDMR_BSMA1516;
132 * Issue PRECHARGE ALL command.
134 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
137 ppcDcbf((unsigned long) sdram_addr);
141 * Issue 8 AUTO REFRESH commands.
143 for (idx = 0; idx < 8; idx++) {
144 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
147 ppcDcbf((unsigned long) sdram_addr);
152 * Issue 8 MODE-set command.
154 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
157 ppcDcbf((unsigned long) sdram_addr);
161 * Issue NORMAL OP command.
163 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
166 ppcDcbf((unsigned long) sdram_addr);
167 udelay(200); /* Overkill. Must wait > 200 bus cycles */
169 #endif /* enable SDRAM init */