1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
13 #include <asm/processor.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_pci.h>
17 #include <fsl_ddr_sdram.h>
18 #include <asm/fsl_serdes.h>
20 #include <linux/delay.h>
21 #include <linux/libfdt.h>
22 #include <fdt_support.h>
27 #include "../common/cadmus.h"
28 #include "../common/eeprom.h"
29 #include "../common/via.h"
31 void local_bus_init(void);
35 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
36 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
38 /* PCI slot in USER bits CSR[6:7] by convention. */
39 uint pci_slot = get_pci_slot ();
41 uint cpu_board_rev = get_cpu_board_revision ();
43 puts("Board: MPC8548CDS");
44 printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
45 get_board_version(), pci_slot);
46 printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
47 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
48 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
50 * Initialize local bus.
55 * Hack TSEC 3 and 4 IO voltages.
57 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
59 ecm->eedr = 0xffffffff; /* clear ecm errors */
60 ecm->eeer = 0xffffffff; /* enable ecm errors */
65 * Initialize Local Bus
70 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
71 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
76 get_sys_info(&sysinfo);
77 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
79 gur->lbiuiplldcr1 = 0x00078080;
81 gur->lbiuiplldcr0 = 0x7c0f1bf0;
82 } else if (clkdiv == 8) {
83 gur->lbiuiplldcr0 = 0x6c0f1bf0;
84 } else if (clkdiv == 4) {
85 gur->lbiuiplldcr0 = 0x5c0f1bf0;
88 lbc->lcrr |= 0x00030000;
90 asm("sync;isync;msync");
92 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
93 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
97 * Initialize SDRAM memory on the Local Bus.
99 void lbc_sdram_init(void)
101 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
104 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
105 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
109 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
113 * Setup SDRAM Base and Option Registers
115 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
116 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
117 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
120 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
121 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
125 * MPC8548 uses "new" 15-16 style addressing.
127 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
128 lsdmr_common |= LSDMR_BSMA1516;
131 * Issue PRECHARGE ALL command.
133 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
136 ppcDcbf((unsigned long) sdram_addr);
140 * Issue 8 AUTO REFRESH commands.
142 for (idx = 0; idx < 8; idx++) {
143 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
146 ppcDcbf((unsigned long) sdram_addr);
151 * Issue 8 MODE-set command.
153 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
156 ppcDcbf((unsigned long) sdram_addr);
160 * Issue NORMAL OP command.
162 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
165 ppcDcbf((unsigned long) sdram_addr);
166 udelay(200); /* Overkill. Must wait > 200 bus cycles */
168 #endif /* enable SDRAM init */
171 void configure_rgmii(void)
175 /* Change the resistors for the PHY */
176 /* This is needed to get the RGMII working for the 1.3+
178 if (get_board_version() == 0x13) {
179 miiphy_write(DEFAULT_MII_NAME,
180 TSEC1_PHY_ADDR, 29, 18);
182 miiphy_read(DEFAULT_MII_NAME,
183 TSEC1_PHY_ADDR, 30, &temp);
185 temp = (temp & 0xf03f);
186 temp |= 2 << 9; /* 36 ohm */
187 temp |= 2 << 6; /* 39 ohm */
189 miiphy_write(DEFAULT_MII_NAME,
190 TSEC1_PHY_ADDR, 30, temp);
192 miiphy_write(DEFAULT_MII_NAME,
193 TSEC1_PHY_ADDR, 29, 3);
195 miiphy_write(DEFAULT_MII_NAME,
196 TSEC1_PHY_ADDR, 30, 0x8000);
202 int board_eth_init(struct bd_info *bis)
204 #ifdef CONFIG_TSEC_ENET
205 struct fsl_pq_mdio_info mdio_info;
206 struct tsec_info_struct tsec_info[4];
210 SET_STD_TSEC_INFO(tsec_info[num], 1);
214 SET_STD_TSEC_INFO(tsec_info[num], 2);
218 /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
219 if (get_board_version() >= 0x13) {
220 SET_STD_TSEC_INFO(tsec_info[num], 3);
221 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
226 /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
227 if (get_board_version() >= 0x13) {
228 SET_STD_TSEC_INFO(tsec_info[num], 4);
229 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
235 printf("No TSECs initialized\n");
240 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
241 mdio_info.name = DEFAULT_MII_NAME;
242 fsl_pq_mdio_init(bis, &mdio_info);
244 tsec_eth_init(bis, tsec_info, num);
248 return pci_eth_init(bis);