2 * Copyright 2004, 2007 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/immap_fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <spd_sdram.h>
35 #include <fdt_support.h>
37 #include "../common/cadmus.h"
38 #include "../common/eeprom.h"
39 #include "../common/via.h"
41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
42 extern void ddr_enable_ecc(unsigned int dram_size);
45 DECLARE_GLOBAL_DATA_PTR;
47 void local_bus_init(void);
48 void sdram_init(void);
52 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
53 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
55 /* PCI slot in USER bits CSR[6:7] by convention. */
56 uint pci_slot = get_pci_slot ();
58 uint cpu_board_rev = get_cpu_board_revision ();
61 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
62 get_board_version (), pci_slot);
64 printf ("CPU Board Revision %d.%d (0x%04x)\n",
65 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
66 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
68 * Initialize local bus.
75 * Fix CPU2 errata: A core hang possible while executing a
76 * msync instruction and a snoopable transaction from an I/O
77 * master tagged to make quick forward progress is present.
78 * Fixed in Silicon Rev.2.1
80 if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
81 ecm->eebpcr |= (1 << 16);
84 * Hack TSEC 3 and 4 IO voltages.
86 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
88 ecm->eedr = 0xffffffff; /* clear ecm errors */
89 ecm->eeer = 0xffffffff; /* enable ecm errors */
94 initdram(int board_type)
98 puts("Initializing\n");
100 #if defined(CONFIG_DDR_DLL)
103 * Work around to stabilize DDR DLL MSYNC_IN.
104 * Errata DDR9 seems to have been fixed.
105 * This is now the workaround for Errata DDR11:
106 * Override DLL = 1, Course Adj = 1, Tap Select = 0
109 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
111 gur->ddrdllcr = 0x81000000;
112 asm("sync;isync;msync");
117 dram_size = fsl_ddr_sdram();
118 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
119 dram_size *= 0x100000;
121 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
123 * Initialize and enable DDR ECC.
125 ddr_enable_ecc(dram_size);
129 * SDRAM Initialization
138 * Initialize Local Bus
143 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
144 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
150 get_sys_info(&sysinfo);
151 clkdiv = (lbc->lcrr & 0x0f) * 2;
152 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
154 gur->lbiuiplldcr1 = 0x00078080;
156 gur->lbiuiplldcr0 = 0x7c0f1bf0;
157 } else if (clkdiv == 8) {
158 gur->lbiuiplldcr0 = 0x6c0f1bf0;
159 } else if (clkdiv == 4) {
160 gur->lbiuiplldcr0 = 0x5c0f1bf0;
163 lbc->lcrr |= 0x00030000;
165 asm("sync;isync;msync");
167 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
168 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
172 * Initialize SDRAM memory on the Local Bus.
177 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
180 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
181 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
187 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
190 * Setup SDRAM Base and Option Registers
192 lbc->or2 = CONFIG_SYS_OR2_PRELIM;
195 lbc->br2 = CONFIG_SYS_BR2_PRELIM;
198 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
202 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
203 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
207 * MPC8548 uses "new" 15-16 style addressing.
209 cpu_board_rev = get_cpu_board_revision();
210 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
211 lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
214 * Issue PRECHARGE ALL command.
216 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
219 ppcDcbf((unsigned long) sdram_addr);
223 * Issue 8 AUTO REFRESH commands.
225 for (idx = 0; idx < 8; idx++) {
226 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
229 ppcDcbf((unsigned long) sdram_addr);
234 * Issue 8 MODE-set command.
236 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
239 ppcDcbf((unsigned long) sdram_addr);
243 * Issue NORMAL OP command.
245 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
248 ppcDcbf((unsigned long) sdram_addr);
249 udelay(200); /* Overkill. Must wait > 200 bus cycles */
251 #endif /* enable SDRAM init */
254 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
255 /* For some reason the Tundra PCI bridge shows up on itself as a
256 * different device. Work around that by refusing to configure it.
258 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
260 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
261 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
262 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
263 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
264 mpc85xx_config_via_usbide, {0,0,0}},
265 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
266 mpc85xx_config_via_usb, {0,0,0}},
267 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
268 mpc85xx_config_via_usb2, {0,0,0}},
269 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
270 mpc85xx_config_via_power, {0,0,0}},
271 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
272 mpc85xx_config_via_ac97, {0,0,0}},
276 static struct pci_controller pci1_hose = {
277 config_table: pci_mpc85xxcds_config_table};
278 #endif /* CONFIG_PCI */
281 static struct pci_controller pci2_hose;
282 #endif /* CONFIG_PCI2 */
285 static struct pci_controller pcie1_hose;
286 #endif /* CONFIG_PCIE1 */
288 int first_free_busno=0;
293 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
294 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
295 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
300 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
301 extern void fsl_pci_init(struct pci_controller *hose);
302 struct pci_controller *hose = &pci1_hose;
303 struct pci_config_table *table;
305 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
306 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
307 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
309 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
311 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
313 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
314 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
316 (pci_speed == 33333000) ? "33" :
317 (pci_speed == 66666000) ? "66" : "unknown",
318 pci_clk_sel ? "sync" : "async",
319 pci_agent ? "agent" : "host",
320 pci_arb ? "arbiter" : "external-arbiter"
325 pci_set_region(hose->regions + 0,
326 CONFIG_SYS_PCI_MEMORY_BUS,
327 CONFIG_SYS_PCI_MEMORY_PHYS,
328 CONFIG_SYS_PCI_MEMORY_SIZE,
329 PCI_REGION_MEM | PCI_REGION_MEMORY);
332 /* outbound memory */
333 pci_set_region(hose->regions + 1,
334 CONFIG_SYS_PCI1_MEM_BASE,
335 CONFIG_SYS_PCI1_MEM_PHYS,
336 CONFIG_SYS_PCI1_MEM_SIZE,
340 pci_set_region(hose->regions + 2,
341 CONFIG_SYS_PCI1_IO_BASE,
342 CONFIG_SYS_PCI1_IO_PHYS,
343 CONFIG_SYS_PCI1_IO_SIZE,
345 hose->region_count = 3;
347 /* relocate config table pointers */
348 hose->config_table = \
349 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
350 for (table = hose->config_table; table && table->vendor; table++)
351 table->config_device += gd->reloc_off;
353 hose->first_busno=first_free_busno;
354 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
357 first_free_busno=hose->last_busno+1;
358 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
359 #ifdef CONFIG_PCIX_CHECK
360 if (!(gur->pordevsr & PORDEVSR_PCI)) {
362 if (CONFIG_SYS_CLK_FREQ < 66000000)
363 printf("PCI-X will only work at 66 MHz\n");
365 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
366 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
367 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
371 printf (" PCI: disabled\n");
375 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
380 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
381 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
383 printf (" PCI2: 32 bit, 66 MHz, %s\n",
384 pci2_clk_sel ? "sync" : "async");
386 printf (" PCI2: disabled\n");
390 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
391 #endif /* CONFIG_PCI2 */
395 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
396 extern void fsl_pci_init(struct pci_controller *hose);
397 struct pci_controller *hose = &pcie1_hose;
398 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
400 int pcie_configured = io_sel >= 1;
402 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
403 printf ("\n PCIE connected to slot as %s (base address %x)",
404 pcie_ep ? "End Point" : "Root Complex",
407 if (pci->pme_msg_det) {
408 pci->pme_msg_det = 0xffffffff;
409 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
414 pci_set_region(hose->regions + 0,
415 CONFIG_SYS_PCI_MEMORY_BUS,
416 CONFIG_SYS_PCI_MEMORY_PHYS,
417 CONFIG_SYS_PCI_MEMORY_SIZE,
418 PCI_REGION_MEM | PCI_REGION_MEMORY);
420 /* outbound memory */
421 pci_set_region(hose->regions + 1,
422 CONFIG_SYS_PCIE1_MEM_BASE,
423 CONFIG_SYS_PCIE1_MEM_PHYS,
424 CONFIG_SYS_PCIE1_MEM_SIZE,
428 pci_set_region(hose->regions + 2,
429 CONFIG_SYS_PCIE1_IO_BASE,
430 CONFIG_SYS_PCIE1_IO_PHYS,
431 CONFIG_SYS_PCIE1_IO_SIZE,
434 hose->region_count = 3;
436 hose->first_busno=first_free_busno;
437 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
440 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
442 first_free_busno=hose->last_busno+1;
445 printf (" PCIE: disabled\n");
449 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
454 int last_stage_init(void)
458 /* Change the resistors for the PHY */
459 /* This is needed to get the RGMII working for the 1.3+
461 if (get_board_version() == 0x13) {
462 miiphy_write(CONFIG_TSEC1_NAME,
463 TSEC1_PHY_ADDR, 29, 18);
465 miiphy_read(CONFIG_TSEC1_NAME,
466 TSEC1_PHY_ADDR, 30, &temp);
468 temp = (temp & 0xf03f);
469 temp |= 2 << 9; /* 36 ohm */
470 temp |= 2 << 6; /* 39 ohm */
472 miiphy_write(CONFIG_TSEC1_NAME,
473 TSEC1_PHY_ADDR, 30, temp);
475 miiphy_write(CONFIG_TSEC1_NAME,
476 TSEC1_PHY_ADDR, 29, 3);
478 miiphy_write(CONFIG_TSEC1_NAME,
479 TSEC1_PHY_ADDR, 30, 0x8000);
486 #if defined(CONFIG_OF_BOARD_SETUP)
488 ft_pci_setup(void *blob, bd_t *bd)
493 node = fdt_path_offset(blob, "/aliases");
497 path = fdt_getprop(blob, node, "pci0", NULL);
499 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
500 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
504 path = fdt_getprop(blob, node, "pci1", NULL);
506 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
507 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);