board/freescale/mpc8548cds/init.S

   1 /*
   2  * Copyright 2004, 2007 Freescale Semiconductor.
   3  * Copyright 2002,2003, Motorola Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <ppc_asm.tmpl>
  25 #include <ppc_defs.h>
  26 #include <asm/cache.h>
  27 #include <asm/mmu.h>
  28 #include <config.h>
  29 #include <mpc85xx.h>
  30
  31 /*
  32  * TLB0 and TLB1 Entries
  33  *
  34  * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  35  * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  36  * these TLB entries are established.
  37  *
  38  * The TLB entries for DDR are dynamically setup in spd_sdram()
  39  * and use TLB1 Entries 8 through 15 as needed according to the
  40  * size of DDR memory.
  41  *
  42  * MAS0: tlbsel, esel, nv
  43  * MAS1: valid, iprot, tid, ts, tsize
  44  * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  45  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  46  */
  47
  48 #define entry_start \
  49         mflr    r1      ;       \
  50         bl      0f      ;
  51
  52 #define entry_end \
  53 0:      mflr    r0      ;       \
  54         mtlr    r1      ;       \
  55         blr             ;
  56
  57
  58         .section        .bootpg, "ax"
  59         .globl  tlb1_entry
  60 tlb1_entry:
  61         entry_start
  62
  63         /*
  64          * Number of TLB0 and TLB1 entries in the following table
  65          */
  66         .long (2f-1f)/16
  67
  68 1:
  69 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  70         /*
  71          * TLB0         4K      Non-cacheable, guarded
  72          * 0xff700000   4K      Initial CCSRBAR mapping
  73          *
  74          * This ends up at a TLB0 Index==0 entry, and must not collide
  75          * with other TLB0 Entries.
  76          */
  77         .long TLB1_MAS0(0, 0, 0)
  78         .long TLB1_MAS1(1, 0, 0, 0, 0)
  79         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
  80         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
  81 #else
  82 #error("Update the number of table entries in tlb1_entry")
  83 #endif
  84
  85         /*
  86          * TLB0         16K     Cacheable, guarded
  87          * Temporary Global data for initialization
  88          *
  89          * Use four 4K TLB0 entries.  These entries must be cacheable
  90          * as they provide the bootstrap memory before the memory
  91          * controler and real memory have been configured.
  92          *
  93          * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
  94          * and must not collide with other TLB0 entries.
  95          */
  96         .long TLB1_MAS0(0, 0, 0)
  97         .long TLB1_MAS1(1, 0, 0, 0, 0)
  98         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
  99                         0,0,0,0,0,0,1,0)
 100         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
 101                         0,0,0,0,0,1,0,1,0,1)
 102
 103         .long TLB1_MAS0(0, 0, 0)
 104         .long TLB1_MAS1(1, 0, 0, 0, 0)
 105         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 106                         0,0,0,0,0,0,1,0)
 107         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 108                         0,0,0,0,0,1,0,1,0,1)
 109
 110         .long TLB1_MAS0(0, 0, 0)
 111         .long TLB1_MAS1(1, 0, 0, 0, 0)
 112         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 113                         0,0,0,0,0,0,1,0)
 114         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 115                         0,0,0,0,0,1,0,1,0,1)
 116
 117         .long TLB1_MAS0(0, 0, 0)
 118         .long TLB1_MAS1(1, 0, 0, 0, 0)
 119         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 120                         0,0,0,0,0,0,1,0)
 121         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 122                         0,0,0,0,0,1,0,1,0,1)
 123
 124
 125         /*
 126          * TLB 0:       16M     Non-cacheable, guarded
 127          * 0xff000000   16M     FLASH
 128          * Out of reset this entry is only 4K.
 129          */
 130         .long TLB1_MAS0(1, 0, 0)
 131         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
 132         .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
 133         .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
 134
 135         /*
 136          * TLB 1:       1G      Non-cacheable, guarded
 137          * 0x80000000   1G      PCI1/PCIE  8,9,a,b
 138          */
 139         .long TLB1_MAS0(1, 1, 0)
 140         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
 141         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
 142         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
 143
 144 #ifdef CFG_RIO_MEM_PHYS
 145         /*
 146          * TLB 2:       256M    Non-cacheable, guarded
 147          */
 148         .long TLB1_MAS0(1, 2, 0)
 149         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 150         .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
 151                         0,0,0,0,1,0,1,0)
 152         .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
 153
 154         /*
 155          * TLB 3:       256M    Non-cacheable, guarded
 156          */
 157         .long TLB1_MAS0(1, 3, 0)
 158         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 159         .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
 160                         0,0,0,0,1,0,1,0)
 161         .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
 162                         0,0,0,0,0,1,0,1,0,1)
 163 #endif
 164         /*
 165          * TLB 5:       64M     Non-cacheable, guarded
 166          * 0xe000_0000  1M      CCSRBAR
 167          * 0xe200_0000  1M      PCI1 IO
 168          * 0xe210_0000  1M      PCI2 IO
 169          * 0xe300_0000  1M      PCIe IO
 170          */
 171         .long TLB1_MAS0(1, 5, 0)
 172         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 173         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
 174         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
 175
 176         /*
 177          * TLB 6:       64M     Cacheable, non-guarded
 178          * 0xf000_0000  64M     LBC SDRAM
 179          */
 180         .long TLB1_MAS0(1, 6, 0)
 181         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 182         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
 183         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
 184
 185         /*
 186          * TLB 7:       64M     Non-cacheable, guarded
 187          * 0xf8000000   64M     CADMUS registers, relocated L2SRAM
 188          */
 189         .long TLB1_MAS0(1, 7, 0)
 190         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 191         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
 192         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
 193
 194 2:
 195         entry_end
 196
 197 /*
 198  * LAW(Local Access Window) configuration:
 199  *
 200  * 0x0000_0000     0x7fff_ffff     DDR                     2G
 201  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
 202  * 0xa000_0000     0xbfff_ffff     PCIe MEM                512M
 203  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
 204  * 0xe000_0000     0xe000_ffff     CCSR                    1M
 205  * 0xe200_0000     0xe10f_ffff     PCI1 IO                 1M
 206  * 0xe280_0000     0xe20f_ffff     PCI2 IO                 1M
 207  * 0xe300_0000     0xe30f_ffff     PCIe IO                 1M
 208  * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
 209  * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
 210  * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
 211  * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
 212  *
 213  * Notes:
 214  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 215  *    If flash is 8M at default position (last 8M), no LAW needed.
 216  *
 217  * LAW 0 is reserved for boot mapping
 218  */
 219
 220         .section .bootpg, "ax"
 221         .globl  law_entry
 222 law_entry:
 223         entry_start
 224
 225         .long (4f-3f)/8
 226 3:
 227         .long  0
 228         .long  (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 229
 230 #ifdef CFG_PCI1_MEM_PHYS
 231         .long   (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
 232         .long   LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 233
 234         .long   (CFG_PCI1_IO_PHYS>>12) & 0xfffff
 235         .long   LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 236 #endif
 237
 238 #ifdef CFG_PCI2_MEM_PHYS
 239         .long   (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
 240         .long   LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 241
 242         .long   (CFG_PCI2_IO_PHYS>>12) & 0xfffff
 243         .long   LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 244 #endif
 245
 246 #ifdef CFG_PCIE1_MEM_PHYS
 247         .long   (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
 248         .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 249
 250         .long   (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
 251         .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 252 #endif
 253
 254         /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 255         .long   (CFG_LBC_CACHE_BASE>>12) & 0xfffff
 256         .long   LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 257
 258 #ifdef CFG_RIO_MEM_PHYS
 259         .long   (CFG_RIO_MEM_PHYS>>12) & 0xfffff
 260         .long   LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
 261 #endif
 262 4:
 263         entry_end