2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/immap_fsl_pci.h>
30 #include <asm/fsl_ddr_sdram.h>
34 #include <fdt_support.h>
36 #include "../common/pixis.h"
38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
39 extern void ddr_enable_ecc(unsigned int dram_size);
44 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
45 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
46 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
48 if ((uint)&gur->porpllsr != 0xe00e0000) {
49 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
51 printf ("Board: MPC8544DS, System ID: 0x%02x, "
52 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
53 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
54 in8(PIXIS_BASE + PIXIS_PVER));
56 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
57 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
58 ecm->eedr = 0xffffffff; /* Clear ecm errors */
59 ecm->eeer = 0xffffffff; /* Enable ecm errors */
65 initdram(int board_type)
69 puts("Initializing\n");
71 dram_size = fsl_ddr_sdram();
73 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
75 dram_size *= 0x100000;
77 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
79 * Initialize and enable DDR ECC.
81 ddr_enable_ecc(dram_size);
88 static struct pci_controller pci1_hose;
92 static struct pci_controller pcie1_hose;
96 static struct pci_controller pcie2_hose;
100 static struct pci_controller pcie3_hose;
103 int first_free_busno=0;
108 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
109 uint devdisr = gur->devdisr;
110 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
111 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
113 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
114 devdisr, io_sel, host_agent);
117 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
118 printf (" eTSEC1 is in sgmii mode.\n");
119 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
120 printf (" eTSEC3 is in sgmii mode.\n");
125 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
126 extern void fsl_pci_init(struct pci_controller *hose);
127 struct pci_controller *hose = &pcie3_hose;
128 int pcie_ep = (host_agent == 1);
129 int pcie_configured = io_sel >= 1;
131 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
132 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
133 pcie_ep ? "End Point" : "Root Complex",
135 if (pci->pme_msg_det) {
136 pci->pme_msg_det = 0xffffffff;
137 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
142 pci_set_region(hose->regions + 0,
146 PCI_REGION_MEM | PCI_REGION_MEMORY);
148 /* outbound memory */
149 pci_set_region(hose->regions + 1,
156 pci_set_region(hose->regions + 2,
162 hose->region_count = 3;
163 #ifdef CFG_PCIE3_MEM_BASE2
164 /* outbound memory */
165 pci_set_region(hose->regions + 3,
170 hose->region_count++;
172 hose->first_busno=first_free_busno;
173 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
177 first_free_busno=hose->last_busno+1;
178 printf (" PCIE3 on bus %02x - %02x\n",
179 hose->first_busno,hose->last_busno);
182 * Activate ULI1575 legacy chip by performing a fake
183 * memory access. Needed to make ULI RTC work.
185 in_be32((u32 *)CFG_PCIE3_MEM_BASE);
187 printf (" PCIE3: disabled\n");
192 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
197 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
198 extern void fsl_pci_init(struct pci_controller *hose);
199 struct pci_controller *hose = &pcie1_hose;
200 int pcie_ep = (host_agent == 5);
201 int pcie_configured = io_sel & 6;
203 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
204 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
205 pcie_ep ? "End Point" : "Root Complex",
207 if (pci->pme_msg_det) {
208 pci->pme_msg_det = 0xffffffff;
209 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
214 pci_set_region(hose->regions + 0,
218 PCI_REGION_MEM | PCI_REGION_MEMORY);
220 /* outbound memory */
221 pci_set_region(hose->regions + 1,
228 pci_set_region(hose->regions + 2,
234 hose->region_count = 3;
235 #ifdef CFG_PCIE1_MEM_BASE2
236 /* outbound memory */
237 pci_set_region(hose->regions + 3,
242 hose->region_count++;
244 hose->first_busno=first_free_busno;
246 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
250 first_free_busno=hose->last_busno+1;
251 printf(" PCIE1 on bus %02x - %02x\n",
252 hose->first_busno,hose->last_busno);
255 printf (" PCIE1: disabled\n");
260 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
265 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
266 extern void fsl_pci_init(struct pci_controller *hose);
267 struct pci_controller *hose = &pcie2_hose;
268 int pcie_ep = (host_agent == 3);
269 int pcie_configured = io_sel & 4;
271 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
272 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
273 pcie_ep ? "End Point" : "Root Complex",
275 if (pci->pme_msg_det) {
276 pci->pme_msg_det = 0xffffffff;
277 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
282 pci_set_region(hose->regions + 0,
286 PCI_REGION_MEM | PCI_REGION_MEMORY);
288 /* outbound memory */
289 pci_set_region(hose->regions + 1,
296 pci_set_region(hose->regions + 2,
302 hose->region_count = 3;
303 #ifdef CFG_PCIE2_MEM_BASE2
304 /* outbound memory */
305 pci_set_region(hose->regions + 3,
310 hose->region_count++;
312 hose->first_busno=first_free_busno;
313 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
316 first_free_busno=hose->last_busno+1;
317 printf (" PCIE2 on bus %02x - %02x\n",
318 hose->first_busno,hose->last_busno);
321 printf (" PCIE2: disabled\n");
326 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
332 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
333 extern void fsl_pci_init(struct pci_controller *hose);
334 struct pci_controller *hose = &pci1_hose;
336 uint pci_agent = (host_agent == 6);
337 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
339 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
340 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
343 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
344 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
346 (pci_speed == 33333000) ? "33" :
347 (pci_speed == 66666000) ? "66" : "unknown",
348 pci_clk_sel ? "sync" : "async",
349 pci_agent ? "agent" : "host",
350 pci_arb ? "arbiter" : "external-arbiter",
355 pci_set_region(hose->regions + 0,
359 PCI_REGION_MEM | PCI_REGION_MEMORY);
361 /* outbound memory */
362 pci_set_region(hose->regions + 1,
369 pci_set_region(hose->regions + 2,
374 hose->region_count = 3;
375 #ifdef CFG_PCIE3_MEM_BASE2
376 /* outbound memory */
377 pci_set_region(hose->regions + 3,
382 hose->region_count++;
384 hose->first_busno=first_free_busno;
385 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
388 first_free_busno=hose->last_busno+1;
389 printf ("PCI on bus %02x - %02x\n",
390 hose->first_busno,hose->last_busno);
392 printf (" PCI: disabled\n");
396 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
401 int last_stage_init(void)
408 get_board_sys_clk(ulong dummy)
410 u8 i, go_bit, rd_clks;
413 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
416 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
420 * Only if both go bit and the SCLK bit in VCFGEN0 are set
421 * should we be using the AUX register. Remember, we also set the
422 * GO bit to boot from the alternate bank on the on-board flash
427 i = in8(PIXIS_BASE + PIXIS_AUX);
429 i = in8(PIXIS_BASE + PIXIS_SPD);
431 i = in8(PIXIS_BASE + PIXIS_SPD);
466 #if defined(CONFIG_OF_BOARD_SETUP)
469 ft_board_setup(void *blob, bd_t *bd)
474 ft_cpu_setup(blob, bd);
476 node = fdt_path_offset(blob, "/aliases");
480 path = fdt_getprop(blob, node, "pci0", NULL);
482 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
483 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
487 path = fdt_getprop(blob, node, "pci1", NULL);
489 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
490 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
494 path = fdt_getprop(blob, node, "pci2", NULL);
496 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
497 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
501 path = fdt_getprop(blob, node, "pci3", NULL);
503 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
504 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);