board/freescale/mpc8544ds/mpc8544ds.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/fsl_pci.h>
  30 #include <asm/fsl_ddr_sdram.h>
  31 #include <asm/io.h>
  32 #include <miiphy.h>
  33 #include <libfdt.h>
  34 #include <fdt_support.h>
  35 #include <tsec.h>
  36 #include <netdev.h>
  37
  38 #include "../common/pixis.h"
  39 #include "../common/sgmii_riser.h"
  40
  41 int checkboard (void)
  42 {
  43         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  44         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  45         volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  46         u8 vboot;
  47         u8 *pixis_base = (u8 *)PIXIS_BASE;
  48
  49         if ((uint)&gur->porpllsr != 0xe00e0000) {
  50                 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
  51         }
  52         printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
  53                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  54                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  55                 in_8(pixis_base + PIXIS_PVER));
  56
  57         vboot = in_8(pixis_base + PIXIS_VBOOT);
  58         if (vboot & PIXIS_VBOOT_FMAP)
  59                 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
  60         else
  61                 puts ("Promjet\n");
  62
  63         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  64         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  65         ecm->eedr = 0xffffffff;         /* Clear ecm errors */
  66         ecm->eeer = 0xffffffff;         /* Enable ecm errors */
  67
  68         return 0;
  69 }
  70
  71 phys_size_t
  72 initdram(int board_type)
  73 {
  74         long dram_size = 0;
  75
  76         puts("Initializing\n");
  77
  78         dram_size = fsl_ddr_sdram();
  79
  80         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  81
  82         dram_size *= 0x100000;
  83
  84         puts("    DDR: ");
  85         return dram_size;
  86 }
  87
  88 #ifdef CONFIG_PCI1
  89 static struct pci_controller pci1_hose;
  90 #endif
  91
  92 #ifdef CONFIG_PCIE1
  93 static struct pci_controller pcie1_hose;
  94 #endif
  95
  96 #ifdef CONFIG_PCIE2
  97 static struct pci_controller pcie2_hose;
  98 #endif
  99
 100 #ifdef CONFIG_PCIE3
 101 static struct pci_controller pcie3_hose;
 102 #endif
 103
 104 int first_free_busno=0;
 105
 106 void
 107 pci_init_board(void)
 108 {
 109         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 110         uint devdisr = gur->devdisr;
 111         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 112         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 113
 114         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 115                 devdisr, io_sel, host_agent);
 116
 117         if (io_sel & 1) {
 118                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 119                         printf ("    eTSEC1 is in sgmii mode.\n");
 120                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 121                         printf ("    eTSEC3 is in sgmii mode.\n");
 122         }
 123
 124 #ifdef CONFIG_PCIE3
 125 {
 126         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 127         struct pci_controller *hose = &pcie3_hose;
 128         int pcie_ep = (host_agent == 1);
 129         int pcie_configured  = io_sel >= 6;
 130         struct pci_region *r = hose->regions;
 131
 132         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 133                 printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 134                         pcie_ep ? "End Point" : "Root Complex",
 135                         (uint)pci);
 136                 if (pci->pme_msg_det) {
 137                         pci->pme_msg_det = 0xffffffff;
 138                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 139                 }
 140                 printf ("\n");
 141
 142                 /* inbound */
 143                 r += fsl_pci_setup_inbound_windows(r);
 144
 145                 /* outbound memory */
 146                 pci_set_region(r++,
 147                                CONFIG_SYS_PCIE3_MEM_BUS,
 148                                CONFIG_SYS_PCIE3_MEM_PHYS,
 149                                CONFIG_SYS_PCIE3_MEM_SIZE,
 150                                PCI_REGION_MEM);
 151
 152                 /* outbound io */
 153                 pci_set_region(r++,
 154                                CONFIG_SYS_PCIE3_IO_BUS,
 155                                CONFIG_SYS_PCIE3_IO_PHYS,
 156                                CONFIG_SYS_PCIE3_IO_SIZE,
 157                                PCI_REGION_IO);
 158
 159 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
 160                 /* outbound memory */
 161                 pci_set_region(r++,
 162                                CONFIG_SYS_PCIE3_MEM_BUS2,
 163                                CONFIG_SYS_PCIE3_MEM_PHYS2,
 164                                CONFIG_SYS_PCIE3_MEM_SIZE2,
 165                                PCI_REGION_MEM);
 166 #endif
 167                 hose->region_count = r - hose->regions;
 168                 hose->first_busno=first_free_busno;
 169                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 170
 171                 fsl_pci_init(hose);
 172
 173                 first_free_busno=hose->last_busno+1;
 174                 printf ("    PCIE3 on bus %02x - %02x\n",
 175                         hose->first_busno,hose->last_busno);
 176
 177                 /*
 178                  * Activate ULI1575 legacy chip by performing a fake
 179                  * memory access.  Needed to make ULI RTC work.
 180                  */
 181                 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
 182         } else {
 183                 printf ("    PCIE3: disabled\n");
 184         }
 185
 186  }
 187 #else
 188         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 189 #endif
 190
 191 #ifdef CONFIG_PCIE1
 192  {
 193         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 194         struct pci_controller *hose = &pcie1_hose;
 195         int pcie_ep = (host_agent == 5);
 196         int pcie_configured  = io_sel >= 2;
 197         struct pci_region *r = hose->regions;
 198
 199         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 200                 printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
 201                         pcie_ep ? "End Point" : "Root Complex",
 202                         (uint)pci);
 203                 if (pci->pme_msg_det) {
 204                         pci->pme_msg_det = 0xffffffff;
 205                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 206                 }
 207                 printf ("\n");
 208
 209                 /* inbound */
 210                 r += fsl_pci_setup_inbound_windows(r);
 211
 212                 /* outbound memory */
 213                 pci_set_region(r++,
 214                                CONFIG_SYS_PCIE1_MEM_BUS,
 215                                CONFIG_SYS_PCIE1_MEM_PHYS,
 216                                CONFIG_SYS_PCIE1_MEM_SIZE,
 217                                PCI_REGION_MEM);
 218
 219                 /* outbound io */
 220                 pci_set_region(r++,
 221                                CONFIG_SYS_PCIE1_IO_BUS,
 222                                CONFIG_SYS_PCIE1_IO_PHYS,
 223                                CONFIG_SYS_PCIE1_IO_SIZE,
 224                                PCI_REGION_IO);
 225
 226 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2
 227                 /* outbound memory */
 228                 pci_set_region(r++,
 229                                CONFIG_SYS_PCIE1_MEM_BUS2,
 230                                CONFIG_SYS_PCIE1_MEM_PHYS2,
 231                                CONFIG_SYS_PCIE1_MEM_SIZE2,
 232                                PCI_REGION_MEM);
 233 #endif
 234                 hose->region_count = r - hose->regions;
 235                 hose->first_busno=first_free_busno;
 236
 237                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 238
 239                 fsl_pci_init(hose);
 240
 241                 first_free_busno=hose->last_busno+1;
 242                 printf("    PCIE1 on bus %02x - %02x\n",
 243                        hose->first_busno,hose->last_busno);
 244
 245         } else {
 246                 printf ("    PCIE1: disabled\n");
 247         }
 248
 249  }
 250 #else
 251         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 252 #endif
 253
 254 #ifdef CONFIG_PCIE2
 255  {
 256         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 257         struct pci_controller *hose = &pcie2_hose;
 258         int pcie_ep = (host_agent == 3);
 259         int pcie_configured  = io_sel >= 4;
 260         struct pci_region *r = hose->regions;
 261
 262         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 263                 printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 264                         pcie_ep ? "End Point" : "Root Complex",
 265                         (uint)pci);
 266                 if (pci->pme_msg_det) {
 267                         pci->pme_msg_det = 0xffffffff;
 268                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 269                 }
 270                 printf ("\n");
 271
 272                 /* inbound */
 273                 r += fsl_pci_setup_inbound_windows(r);
 274
 275                 /* outbound memory */
 276                 pci_set_region(r++,
 277                                CONFIG_SYS_PCIE2_MEM_BUS,
 278                                CONFIG_SYS_PCIE2_MEM_PHYS,
 279                                CONFIG_SYS_PCIE2_MEM_SIZE,
 280                                PCI_REGION_MEM);
 281
 282                 /* outbound io */
 283                 pci_set_region(r++,
 284                                CONFIG_SYS_PCIE2_IO_BUS,
 285                                CONFIG_SYS_PCIE2_IO_PHYS,
 286                                CONFIG_SYS_PCIE2_IO_SIZE,
 287                                PCI_REGION_IO);
 288
 289 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2
 290                 /* outbound memory */
 291                 pci_set_region(r++,
 292                                CONFIG_SYS_PCIE2_MEM_BUS2,
 293                                CONFIG_SYS_PCIE2_MEM_PHYS2,
 294                                CONFIG_SYS_PCIE2_MEM_SIZE2,
 295                                PCI_REGION_MEM);
 296 #endif
 297                 hose->region_count = r - hose->regions;
 298                 hose->first_busno=first_free_busno;
 299                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 300
 301                 fsl_pci_init(hose);
 302                 first_free_busno=hose->last_busno+1;
 303                 printf ("    PCIE2 on bus %02x - %02x\n",
 304                         hose->first_busno,hose->last_busno);
 305
 306         } else {
 307                 printf ("    PCIE2: disabled\n");
 308         }
 309
 310  }
 311 #else
 312         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 313 #endif
 314
 315
 316 #ifdef CONFIG_PCI1
 317 {
 318         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 319         struct pci_controller *hose = &pci1_hose;
 320         struct pci_region *r = hose->regions;
 321
 322         uint pci_agent = (host_agent == 6);
 323         uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
 324         uint pci_32 = 1;
 325         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 326         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 327
 328
 329         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 330                 printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
 331                         (pci_32) ? 32 : 64,
 332                         (pci_speed == 33333000) ? "33" :
 333                         (pci_speed == 66666000) ? "66" : "unknown",
 334                         pci_clk_sel ? "sync" : "async",
 335                         pci_agent ? "agent" : "host",
 336                         pci_arb ? "arbiter" : "external-arbiter",
 337                         (uint)pci
 338                         );
 339
 340                 /* inbound */
 341                 r += fsl_pci_setup_inbound_windows(r);
 342
 343                 /* outbound memory */
 344                 pci_set_region(r++,
 345                                CONFIG_SYS_PCI1_MEM_BUS,
 346                                CONFIG_SYS_PCI1_MEM_PHYS,
 347                                CONFIG_SYS_PCI1_MEM_SIZE,
 348                                PCI_REGION_MEM);
 349
 350                 /* outbound io */
 351                 pci_set_region(r++,
 352                                CONFIG_SYS_PCI1_IO_BUS,
 353                                CONFIG_SYS_PCI1_IO_PHYS,
 354                                CONFIG_SYS_PCI1_IO_SIZE,
 355                                PCI_REGION_IO);
 356
 357 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
 358                 /* outbound memory */
 359                 pci_set_region(r++,
 360                                CONFIG_SYS_PCIE3_MEM_BUS2,
 361                                CONFIG_SYS_PCIE3_MEM_PHYS2,
 362                                CONFIG_SYS_PCIE3_MEM_SIZE2,
 363                                PCI_REGION_MEM);
 364 #endif
 365                 hose->region_count = r - hose->regions;
 366                 hose->first_busno=first_free_busno;
 367                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 368
 369                 fsl_pci_init(hose);
 370                 first_free_busno=hose->last_busno+1;
 371                 printf ("PCI on bus %02x - %02x\n",
 372                         hose->first_busno,hose->last_busno);
 373         } else {
 374                 printf ("    PCI: disabled\n");
 375         }
 376 }
 377 #else
 378         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 379 #endif
 380 }
 381
 382
 383 int last_stage_init(void)
 384 {
 385         return 0;
 386 }
 387
 388
 389 unsigned long
 390 get_board_sys_clk(ulong dummy)
 391 {
 392         u8 i, go_bit, rd_clks;
 393         ulong val = 0;
 394         u8 *pixis_base = (u8 *)PIXIS_BASE;
 395
 396         go_bit = in_8(pixis_base + PIXIS_VCTL);
 397         go_bit &= 0x01;
 398
 399         rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
 400         rd_clks &= 0x1C;
 401
 402         /*
 403          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 404          * should we be using the AUX register. Remember, we also set the
 405          * GO bit to boot from the alternate bank on the on-board flash
 406          */
 407
 408         if (go_bit) {
 409                 if (rd_clks == 0x1c)
 410                         i = in_8(pixis_base + PIXIS_AUX);
 411                 else
 412                         i = in_8(pixis_base + PIXIS_SPD);
 413         } else {
 414                 i = in_8(pixis_base + PIXIS_SPD);
 415         }
 416
 417         i &= 0x07;
 418
 419         switch (i) {
 420         case 0:
 421                 val = 33333333;
 422                 break;
 423         case 1:
 424                 val = 40000000;
 425                 break;
 426         case 2:
 427                 val = 50000000;
 428                 break;
 429         case 3:
 430                 val = 66666666;
 431                 break;
 432         case 4:
 433                 val = 83000000;
 434                 break;
 435         case 5:
 436                 val = 100000000;
 437                 break;
 438         case 6:
 439                 val = 133333333;
 440                 break;
 441         case 7:
 442                 val = 166666666;
 443                 break;
 444         }
 445
 446         return val;
 447 }
 448
 449 int board_eth_init(bd_t *bis)
 450 {
 451 #ifdef CONFIG_TSEC_ENET
 452         struct tsec_info_struct tsec_info[2];
 453         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 454         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 455         int num = 0;
 456
 457 #ifdef CONFIG_TSEC1
 458         SET_STD_TSEC_INFO(tsec_info[num], 1);
 459         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 460                 tsec_info[num].flags |= TSEC_SGMII;
 461         num++;
 462 #endif
 463 #ifdef CONFIG_TSEC3
 464         SET_STD_TSEC_INFO(tsec_info[num], 3);
 465         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 466                 tsec_info[num].flags |= TSEC_SGMII;
 467         num++;
 468 #endif
 469
 470         if (!num) {
 471                 printf("No TSECs initialized\n");
 472
 473                 return 0;
 474         }
 475
 476         if (io_sel & 1)
 477                 fsl_sgmii_riser_init(tsec_info, num);
 478
 479
 480         tsec_eth_init(bis, tsec_info, num);
 481 #endif
 482         return pci_eth_init(bis);
 483 }
 484
 485 #if defined(CONFIG_OF_BOARD_SETUP)
 486 void ft_board_setup(void *blob, bd_t *bd)
 487 {
 488         ft_cpu_setup(blob, bd);
 489
 490
 491 #ifdef CONFIG_PCI1
 492         ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 493 #endif
 494 #ifdef CONFIG_PCIE2
 495         ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
 496 #endif
 497 #ifdef CONFIG_PCIE1
 498         ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
 499 #endif
 500 #ifdef CONFIG_PCIE3
 501         ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
 502 #endif
 503 #ifdef CONFIG_FSL_SGMII_RISER
 504         fsl_sgmii_riser_fdt_fixup(blob);
 505 #endif
 506 }
 507 #endif