2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/fsl_pci.h>
30 #include <asm/fsl_ddr_sdram.h>
31 #include <asm/fsl_serdes.h>
35 #include <fdt_support.h>
39 #include "../common/sgmii_riser.h"
43 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
44 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
45 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
47 u8 *pixis_base = (u8 *)PIXIS_BASE;
49 if ((uint)&gur->porpllsr != 0xe00e0000) {
50 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
52 printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
54 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
55 in_8(pixis_base + PIXIS_PVER));
57 vboot = in_8(pixis_base + PIXIS_VBOOT);
58 if (vboot & PIXIS_VBOOT_FMAP)
59 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
63 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
64 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
65 ecm->eedr = 0xffffffff; /* Clear ecm errors */
66 ecm->eeer = 0xffffffff; /* Enable ecm errors */
72 static struct pci_controller pci1_hose;
76 static struct pci_controller pcie1_hose;
80 static struct pci_controller pcie2_hose;
84 static struct pci_controller pcie3_hose;
87 void pci_init_board(void)
89 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
90 struct fsl_pci_info pci_info[4];
91 u32 devdisr, pordevsr, io_sel;
92 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
93 int first_free_busno = 0;
96 int pcie_ep, pcie_configured;
98 devdisr = in_be32(&gur->devdisr);
99 pordevsr = in_be32(&gur->pordevsr);
100 porpllsr = in_be32(&gur->porpllsr);
101 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
103 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
108 pcie_configured = is_serdes_configured(PCIE3);
110 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
111 SET_STD_PCIE_INFO(pci_info[num], 3);
112 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
113 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
114 /* outbound memory */
115 pci_set_region(&pcie3_hose.regions[0],
116 CONFIG_SYS_PCIE3_MEM_BUS2,
117 CONFIG_SYS_PCIE3_MEM_PHYS2,
118 CONFIG_SYS_PCIE3_MEM_SIZE2,
121 pcie3_hose.region_count = 1;
123 printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
124 pcie_ep ? "Endpoint" : "Root Complex",
126 first_free_busno = fsl_pci_init_port(&pci_info[num++],
127 &pcie3_hose, first_free_busno);
130 * Activate ULI1575 legacy chip by performing a fake
131 * memory access. Needed to make ULI RTC work.
133 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
135 printf("PCIE3: disabled\n");
139 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
143 pcie_configured = is_serdes_configured(PCIE1);
145 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
146 SET_STD_PCIE_INFO(pci_info[num], 1);
147 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
148 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2
149 /* outbound memory */
150 pci_set_region(&pcie1_hose.regions[0],
151 CONFIG_SYS_PCIE1_MEM_BUS2,
152 CONFIG_SYS_PCIE1_MEM_PHYS2,
153 CONFIG_SYS_PCIE1_MEM_SIZE2,
156 pcie1_hose.region_count = 1;
158 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
159 pcie_ep ? "Endpoint" : "Root Complex",
162 first_free_busno = fsl_pci_init_port(&pci_info[num++],
163 &pcie1_hose, first_free_busno);
165 printf("PCIE1: disabled\n");
170 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
174 pcie_configured = is_serdes_configured(PCIE2);
176 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
177 SET_STD_PCIE_INFO(pci_info[num], 2);
178 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
179 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2
180 /* outbound memory */
181 pci_set_region(&pcie2_hose.regions[0],
182 CONFIG_SYS_PCIE2_MEM_BUS2,
183 CONFIG_SYS_PCIE2_MEM_PHYS2,
184 CONFIG_SYS_PCIE2_MEM_SIZE2,
187 pcie2_hose.region_count = 1;
189 printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
190 pcie_ep ? "Endpoint" : "Root Complex",
192 first_free_busno = fsl_pci_init_port(&pci_info[num++],
193 &pcie2_hose, first_free_busno);
195 printf("PCIE2: disabled\n");
200 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
204 pci_speed = 66666000;
206 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
207 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
209 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
210 SET_STD_PCI_INFO(pci_info[num], 1);
211 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
212 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
214 (pci_speed == 33333000) ? "33" :
215 (pci_speed == 66666000) ? "66" : "unknown",
216 pci_clk_sel ? "sync" : "async",
217 pci_agent ? "agent" : "host",
218 pci_arb ? "arbiter" : "external-arbiter",
221 first_free_busno = fsl_pci_init_port(&pci_info[num++],
222 &pci1_hose, first_free_busno);
224 printf("PCI: disabled\n");
229 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
234 int last_stage_init(void)
241 get_board_sys_clk(ulong dummy)
243 u8 i, go_bit, rd_clks;
245 u8 *pixis_base = (u8 *)PIXIS_BASE;
247 go_bit = in_8(pixis_base + PIXIS_VCTL);
250 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
254 * Only if both go bit and the SCLK bit in VCFGEN0 are set
255 * should we be using the AUX register. Remember, we also set the
256 * GO bit to boot from the alternate bank on the on-board flash
261 i = in_8(pixis_base + PIXIS_AUX);
263 i = in_8(pixis_base + PIXIS_SPD);
265 i = in_8(pixis_base + PIXIS_SPD);
300 int board_eth_init(bd_t *bis)
302 #ifdef CONFIG_TSEC_ENET
303 struct tsec_info_struct tsec_info[2];
307 SET_STD_TSEC_INFO(tsec_info[num], 1);
308 if (is_serdes_configured(SGMII_TSEC1)) {
309 puts("eTSEC1 is in sgmii mode.\n");
310 tsec_info[num].flags |= TSEC_SGMII;
315 SET_STD_TSEC_INFO(tsec_info[num], 3);
316 if (is_serdes_configured(SGMII_TSEC3)) {
317 puts("eTSEC3 is in sgmii mode.\n");
318 tsec_info[num].flags |= TSEC_SGMII;
324 printf("No TSECs initialized\n");
329 if (is_serdes_configured(SGMII_TSEC1) ||
330 is_serdes_configured(SGMII_TSEC3)) {
331 fsl_sgmii_riser_init(tsec_info, num);
335 tsec_eth_init(bis, tsec_info, num);
337 return pci_eth_init(bis);
340 #if defined(CONFIG_OF_BOARD_SETUP)
341 void ft_board_setup(void *blob, bd_t *bd)
343 ft_cpu_setup(blob, bd);
347 #ifdef CONFIG_FSL_SGMII_RISER
348 fsl_sgmii_riser_fdt_fixup(blob);