board/freescale/mpc8544ds/init.S

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <ppc_asm.tmpl>
  24 #include <ppc_defs.h>
  25 #include <asm/cache.h>
  26 #include <asm/mmu.h>
  27 #include <config.h>
  28 #include <mpc85xx.h>
  29
  30 #define LAWAR_TRGT_PCI1         0x00000000
  31 #define LAWAR_TRGT_PCIE1        0x00200000
  32 #define LAWAR_TRGT_PCIE2        0x00100000
  33 #define LAWAR_TRGT_PCIE3        0x00300000
  34 #define LAWAR_TRGT_LBC          0x00400000
  35 #define LAWAR_TRGT_DDR          0x00f00000
  36
  37 /*
  38  * TLB0 and TLB1 Entries
  39  *
  40  * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  41  * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  42  * these TLB entries are established.
  43  *
  44  * The TLB entries for DDR are dynamically setup in spd_sdram()
  45  * and use TLB1 Entries 8 through 15 as needed according to the
  46  * size of DDR memory.
  47  *
  48  * MAS0: tlbsel, esel, nv
  49  * MAS1: valid, iprot, tid, ts, tsize
  50  * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  51  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  52  */
  53
  54 #define entry_start \
  55         mflr    r1      ;       \
  56         bl      0f      ;
  57
  58 #define entry_end \
  59 0:      mflr    r0      ;       \
  60         mtlr    r1      ;       \
  61         blr             ;
  62
  63
  64         .section        .bootpg, "ax"
  65         .globl  tlb1_entry
  66 tlb1_entry:
  67         entry_start
  68
  69         /*
  70          * Number of TLB0 and TLB1 entries in the following table
  71          */
  72         .long (2f-1f)/16
  73 1:
  74         /*
  75          * TLB0         4K      Non-cacheable, guarded
  76          * 0xff700000   4K      Initial CCSRBAR mapping
  77          *
  78          * This ends up at a TLB0 Index==0 entry, and must not collide
  79          * with other TLB0 Entries.
  80          */
  81         .long TLB1_MAS0(0, 0, 0)
  82         .long TLB1_MAS1(1, 0, 0, 0, 0)
  83         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
  84         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
  85
  86         /*
  87          * TLB0         16K     Cacheable, guarded
  88          * Temporary Global data for initialization
  89          *
  90          * Use four 4K TLB0 entries.  These entries must be cacheable
  91          * as they provide the bootstrap memory before the memory
  92          * controler and real memory have been configured.
  93          *
  94          * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
  95          * and must not collide with other TLB0 entries.
  96          */
  97         .long TLB1_MAS0(0, 0, 0)
  98         .long TLB1_MAS1(1, 0, 0, 0, 0)
  99         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
 100                         0,0,0,0,0,0,1,0)
 101         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
 102                         0,0,0,0,0,1,0,1,0,1)
 103
 104         .long TLB1_MAS0(0, 0, 0)
 105         .long TLB1_MAS1(1, 0, 0, 0, 0)
 106         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 107                         0,0,0,0,0,0,1,0)
 108         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 109                         0,0,0,0,0,1,0,1,0,1)
 110
 111         .long TLB1_MAS0(0, 0, 0)
 112         .long TLB1_MAS1(1, 0, 0, 0, 0)
 113         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 114                         0,0,0,0,0,0,1,0)
 115         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 116                         0,0,0,0,0,1,0,1,0,1)
 117
 118         .long TLB1_MAS0(0, 0, 0)
 119         .long TLB1_MAS1(1, 0, 0, 0, 0)
 120         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 121                         0,0,0,0,0,0,1,0)
 122         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 123                         0,0,0,0,0,1,0,1,0,1)
 124
 125
 126         /*
 127          * TLB 0:       64M     Non-cacheable, guarded
 128          * 0xfc000000   64M     Covers FLASH at 0xFE800000 and 0xFF800000
 129          * Out of reset this entry is only 4K.
 130          */
 131         .long TLB1_MAS0(1, 0, 0)
 132         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 133         .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
 134         .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
 135
 136         /*
 137          * TLB 1:       1G      Non-cacheable, guarded
 138          * 0x80000000   1G      PCIE  8,9,a,b
 139          */
 140         .long TLB1_MAS0(1, 1, 0)
 141         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
 142         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCIE_PHYS),
 143                 0,0,0,0,1,0,1,0)
 144         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCIE_PHYS),
 145                 0,0,0,0,0,1,0,1,0,1)
 146
 147         /*
 148          * TLB 2:       256M    Non-cacheable, guarded
 149          */
 150         .long TLB1_MAS0(1, 2, 0)
 151         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 152         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS),
 153                         0,0,0,0,1,0,1,0)
 154         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS),     0,0,0,0,0,1,0,1,0,1)
 155
 156         /*
 157          * TLB 3:       256M    Non-cacheable, guarded
 158          */
 159         .long TLB1_MAS0(1, 3, 0)
 160         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 161         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS + 0x10000000),
 162                         0,0,0,0,1,0,1,0)
 163         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS + 0x10000000),
 164                         0,0,0,0,0,1,0,1,0,1)
 165
 166         /*
 167          * TLB 4:       64M     Non-cacheable, guarded
 168          * 0xe000_0000  1M      CCSRBAR
 169          * 0xe100_0000  255M    PCI IO range
 170          */
 171         .long TLB1_MAS0(1, 4, 0)
 172         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 173         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
 174         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
 175
 176 #ifdef CFG_LBC_CACHE_BASE
 177         /*
 178          * TLB 5:       64M     Cacheable, non-guarded
 179          */
 180         .long TLB1_MAS0(1, 5, 0)
 181         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 182         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
 183         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
 184 #endif
 185         /*
 186          * TLB 6:       64M     Non-cacheable, guarded
 187          * 0xf8000000   64M     PIXIS 0xF8000000 - 0xFBFFFFFF
 188          */
 189         .long TLB1_MAS0(1, 6, 0)
 190         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 191         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
 192         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
 193 2:
 194         entry_end
 195
 196 /*
 197  * LAW(Local Access Window) configuration:
 198  *
 199  *
 200  * Notes:
 201  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 202  *    If flash is 8M at default position (last 8M), no LAW needed.
 203  *
 204  * LAW 0 is reserved for boot mapping
 205  */
 206
 207         .section .bootpg, "ax"
 208         .globl  law_entry
 209 law_entry:
 210         entry_start
 211
 212         .long (4f-3f)/8
 213 3:
 214         .long   0
 215         .long   (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 216
 217         .long   (CFG_PCI1_MEM_BASE>>12) & 0xfffff
 218         .long   LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 219
 220         .long   (CFG_PCI1_IO_PHYS>>12) & 0xfffff
 221         .long   LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)
 222
 223         .long   (CFG_LBC_CACHE_BASE>>12) & 0xfffff
 224         .long   LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 225
 226         .long   (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
 227         .long   LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
 228
 229         /* To keep to 10 LAWs, PCIE1_IO_PHYS must use top of mem region  */
 230
 231         .long   (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
 232         .long   LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 233
 234         .long   (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
 235         .long   LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_16M)
 236
 237         .long   (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
 238         .long   LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_256M)
 239
 240         .long   (CFG_PCIE3_IO_PHYS>>12) & 0xfffff
 241         .long   LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_16M)
 242 4:
 243         entry_end