board/freescale/mpc8544ds/init.S

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <ppc_asm.tmpl>
  24 #include <ppc_defs.h>
  25 #include <asm/cache.h>
  26 #include <asm/mmu.h>
  27 #include <config.h>
  28 #include <mpc85xx.h>
  29
  30 /*
  31  * TLB0 and TLB1 Entries
  32  *
  33  * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  34  * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  35  * these TLB entries are established.
  36  *
  37  * The TLB entries for DDR are dynamically setup in spd_sdram()
  38  * and use TLB1 Entries 8 through 15 as needed according to the
  39  * size of DDR memory.
  40  *
  41  * MAS0: tlbsel, esel, nv
  42  * MAS1: valid, iprot, tid, ts, tsize
  43  * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  44  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  45  */
  46
  47 #define entry_start \
  48         mflr    r1      ;       \
  49         bl      0f      ;
  50
  51 #define entry_end \
  52 0:      mflr    r0      ;       \
  53         mtlr    r1      ;       \
  54         blr             ;
  55
  56
  57         .section        .bootpg, "ax"
  58         .globl  tlb1_entry
  59 tlb1_entry:
  60         entry_start
  61
  62         /*
  63          * Number of TLB0 and TLB1 entries in the following table
  64          */
  65         .long (2f-1f)/16
  66 1:
  67         /*
  68          * TLB0         4K      Non-cacheable, guarded
  69          * 0xff700000   4K      Initial CCSRBAR mapping
  70          *
  71          * This ends up at a TLB0 Index==0 entry, and must not collide
  72          * with other TLB0 Entries.
  73          */
  74         .long TLB1_MAS0(0, 0, 0)
  75         .long TLB1_MAS1(1, 0, 0, 0, 0)
  76         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
  77         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
  78
  79         /*
  80          * TLB0         16K     Cacheable, guarded
  81          * Temporary Global data for initialization
  82          *
  83          * Use four 4K TLB0 entries.  These entries must be cacheable
  84          * as they provide the bootstrap memory before the memory
  85          * controler and real memory have been configured.
  86          *
  87          * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
  88          * and must not collide with other TLB0 entries.
  89          */
  90         .long TLB1_MAS0(0, 0, 0)
  91         .long TLB1_MAS1(1, 0, 0, 0, 0)
  92         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
  93                         0,0,0,0,0,0,1,0)
  94         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
  95                         0,0,0,0,0,1,0,1,0,1)
  96
  97         .long TLB1_MAS0(0, 0, 0)
  98         .long TLB1_MAS1(1, 0, 0, 0, 0)
  99         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 100                         0,0,0,0,0,0,1,0)
 101         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 102                         0,0,0,0,0,1,0,1,0,1)
 103
 104         .long TLB1_MAS0(0, 0, 0)
 105         .long TLB1_MAS1(1, 0, 0, 0, 0)
 106         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 107                         0,0,0,0,0,0,1,0)
 108         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 109                         0,0,0,0,0,1,0,1,0,1)
 110
 111         .long TLB1_MAS0(0, 0, 0)
 112         .long TLB1_MAS1(1, 0, 0, 0, 0)
 113         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 114                         0,0,0,0,0,0,1,0)
 115         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 116                         0,0,0,0,0,1,0,1,0,1)
 117
 118
 119         /*
 120          * TLB 0:       64M     Non-cacheable, guarded
 121          * 0xfc000000   64M     Covers FLASH at 0xFE800000 and 0xFF800000
 122          * Out of reset this entry is only 4K.
 123          */
 124         .long TLB1_MAS0(1, 0, 0)
 125         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 126         .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
 127         .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
 128
 129         /*
 130          * TLB 1:       1G      Non-cacheable, guarded
 131          * 0x80000000   1G      PCIE  8,9,a,b
 132          */
 133         .long TLB1_MAS0(1, 1, 0)
 134         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
 135         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCIE_PHYS),
 136                 0,0,0,0,1,0,1,0)
 137         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCIE_PHYS),
 138                 0,0,0,0,0,1,0,1,0,1)
 139
 140         /*
 141          * TLB 2:       256M    Non-cacheable, guarded
 142          */
 143         .long TLB1_MAS0(1, 2, 0)
 144         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 145         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS),
 146                         0,0,0,0,1,0,1,0)
 147         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS),     0,0,0,0,0,1,0,1,0,1)
 148
 149         /*
 150          * TLB 3:       256M    Non-cacheable, guarded
 151          */
 152         .long TLB1_MAS0(1, 3, 0)
 153         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 154         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS + 0x10000000),
 155                         0,0,0,0,1,0,1,0)
 156         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS + 0x10000000),
 157                         0,0,0,0,0,1,0,1,0,1)
 158
 159         /*
 160          * TLB 4:       64M     Non-cacheable, guarded
 161          * 0xe000_0000  1M      CCSRBAR
 162          * 0xe100_0000  255M    PCI IO range
 163          */
 164         .long TLB1_MAS0(1, 4, 0)
 165         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 166         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
 167         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
 168
 169 #ifdef CFG_LBC_CACHE_BASE
 170         /*
 171          * TLB 5:       64M     Cacheable, non-guarded
 172          */
 173         .long TLB1_MAS0(1, 5, 0)
 174         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 175         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
 176         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
 177 #endif
 178         /*
 179          * TLB 6:       64M     Non-cacheable, guarded
 180          * 0xf8000000   64M     PIXIS 0xF8000000 - 0xFBFFFFFF
 181          */
 182         .long TLB1_MAS0(1, 6, 0)
 183         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 184         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
 185         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
 186 2:
 187         entry_end
 188
 189 /*
 190  * LAW(Local Access Window) configuration:
 191  *
 192  *
 193  * Notes:
 194  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 195  *    If flash is 8M at default position (last 8M), no LAW needed.
 196  *
 197  * LAW 0 is reserved for boot mapping
 198  */
 199
 200         .section .bootpg, "ax"
 201         .globl  law_entry
 202 law_entry:
 203         entry_start
 204
 205         .long (4f-3f)/8
 206 3:
 207         .long   0
 208         .long   (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 209
 210         .long   (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
 211         .long   LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 212
 213         .long   (CFG_PCI1_IO_PHYS>>12) & 0xfffff
 214         .long   LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 215
 216         .long   (CFG_LBC_CACHE_BASE>>12) & 0xfffff
 217         .long   LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 218
 219         .long   (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
 220         .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
 221
 222         .long   (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
 223         .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 224
 225         .long   (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
 226         .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 227
 228         .long   (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
 229         .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 230
 231         /* contains both PCIE3 MEM & IO space */
 232         .long   (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
 233         .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
 234 4:
 235         entry_end