1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
12 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_pci.h>
17 #include <fsl_ddr_sdram.h>
19 #include <asm/fsl_serdes.h>
22 #include <linux/delay.h>
23 #include <linux/libfdt.h>
24 #include <spd_sdram.h>
25 #include <fdt_support.h>
31 #include "../common/sgmii_riser.h"
33 int board_early_init_f (void)
36 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
38 setbits_be32(&gur->pmuxcr,
39 (MPC85xx_PMUXCR_SDHC_CD |
40 MPC85xx_PMUXCR_SDHC_WP));
42 /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
43 * however, this erratum only applies to MPC8536 Rev1.0.
44 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
45 if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
46 (SVR_MIN(get_svr()) >= 0x1))
47 || (SVR_MAJ(get_svr() & 0x7) > 0x1))
48 setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
56 u8 *pixis_base = (u8 *)PIXIS_BASE;
58 printf("Board: MPC8536DS Sys ID: 0x%02x, "
59 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
60 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
61 in_8(pixis_base + PIXIS_PVER));
63 vboot = in_8(pixis_base + PIXIS_VBOOT);
64 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
65 case PIXIS_VBOOT_LBMAP_NOR0:
68 case PIXIS_VBOOT_LBMAP_NOR1:
71 case PIXIS_VBOOT_LBMAP_NOR2:
74 case PIXIS_VBOOT_LBMAP_NOR3:
77 case PIXIS_VBOOT_LBMAP_PJET:
80 case PIXIS_VBOOT_LBMAP_NAND:
88 #if !defined(CONFIG_SPD_EEPROM)
90 * Fixed sdram init -- doesn't use serial presence detect.
93 phys_size_t fixed_sdram (void)
95 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
96 struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
99 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
100 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
102 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
103 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
104 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
105 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
106 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
107 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
108 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
109 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
110 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
111 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
113 #if defined (CONFIG_DDR_ECC)
114 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
115 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
116 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
122 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
124 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
126 debug("DDR - 1st controller: memory initializing\n");
128 * Poll until memory is initialized.
129 * 512 Meg at 400 might hit this 200 times or so.
131 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
134 debug("DDR: memory initialized\n\n");
139 return 512 * 1024 * 1024;
145 static struct pci_controller pci1_hose;
149 void pci_init_board(void)
151 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
152 struct fsl_pci_info pci_info;
153 u32 devdisr, pordevsr;
154 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
155 int first_free_busno;
157 first_free_busno = fsl_pcie_init_board(0);
160 devdisr = in_be32(&gur->devdisr);
161 pordevsr = in_be32(&gur->pordevsr);
162 porpllsr = in_be32(&gur->porpllsr);
164 pci_speed = 66666000;
166 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
167 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
169 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
170 SET_STD_PCI_INFO(pci_info, 1);
171 set_next_law(pci_info.mem_phys,
172 law_size_bits(pci_info.mem_size), pci_info.law);
173 set_next_law(pci_info.io_phys,
174 law_size_bits(pci_info.io_size), pci_info.law);
176 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
177 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
179 (pci_speed == 33333000) ? "33" :
180 (pci_speed == 66666000) ? "66" : "unknown",
181 pci_clk_sel ? "sync" : "async",
182 pci_agent ? "agent" : "host",
183 pci_arb ? "arbiter" : "external-arbiter",
186 first_free_busno = fsl_pci_init_port(&pci_info,
187 &pci1_hose, first_free_busno);
189 printf("PCI: disabled\n");
194 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
199 int board_early_init_r(void)
201 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
202 int flash_esel = find_tlb_idx((void *)flashbase, 1);
205 * Remap Boot flash + PROMJET region to caching-inhibited
206 * so that flash can be erased properly.
209 /* Flush d-cache and invalidate i-cache of any FLASH data */
213 if (flash_esel == -1) {
214 /* very unlikely unless something is messed up */
215 puts("Error: Could not find TLB for FLASH BASE\n");
216 flash_esel = 1; /* give our best effort to continue */
218 /* invalidate existing TLB entry for flash + promjet */
219 disable_tlb(flash_esel);
222 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
223 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
224 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
229 int board_eth_init(bd_t *bis)
231 #ifdef CONFIG_TSEC_ENET
232 struct fsl_pq_mdio_info mdio_info;
233 struct tsec_info_struct tsec_info[2];
237 SET_STD_TSEC_INFO(tsec_info[num], 1);
238 if (is_serdes_configured(SGMII_TSEC1)) {
239 puts("eTSEC1 is in sgmii mode.\n");
240 tsec_info[num].phyaddr = 0;
241 tsec_info[num].flags |= TSEC_SGMII;
246 SET_STD_TSEC_INFO(tsec_info[num], 3);
247 if (is_serdes_configured(SGMII_TSEC3)) {
248 puts("eTSEC3 is in sgmii mode.\n");
249 tsec_info[num].phyaddr = 1;
250 tsec_info[num].flags |= TSEC_SGMII;
256 printf("No TSECs initialized\n");
260 #ifdef CONFIG_FSL_SGMII_RISER
261 if (is_serdes_configured(SGMII_TSEC1) ||
262 is_serdes_configured(SGMII_TSEC3)) {
263 fsl_sgmii_riser_init(tsec_info, num);
267 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
268 mdio_info.name = DEFAULT_MII_NAME;
269 fsl_pq_mdio_init(bis, &mdio_info);
271 tsec_eth_init(bis, tsec_info, num);
273 return pci_eth_init(bis);
276 #if defined(CONFIG_OF_BOARD_SETUP)
277 int ft_board_setup(void *blob, bd_t *bd)
279 ft_cpu_setup(blob, bd);
283 #ifdef CONFIG_FSL_SGMII_RISER
284 fsl_sgmii_riser_fdt_fixup(blob);
287 #ifdef CONFIG_HAS_FSL_MPH_USB
288 fsl_fdt_fixup_dr_usb(blob, bd);