mpc85xx boards: initdram() cleanup/bugfix
[platform/kernel/u-boot.git] / board / freescale / mpc8536ds / mpc8536ds.c
1 /*
2  * Copyright 2008-2010 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22
23 #include <common.h>
24 #include <command.h>
25 #include <pci.h>
26 #include <asm/processor.h>
27 #include <asm/mmu.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <asm/io.h>
33 #include <asm/fsl_serdes.h>
34 #include <spd.h>
35 #include <miiphy.h>
36 #include <libfdt.h>
37 #include <spd_sdram.h>
38 #include <fdt_support.h>
39 #include <tsec.h>
40 #include <netdev.h>
41 #include <sata.h>
42
43 #include "../common/sgmii_riser.h"
44
45 int board_early_init_f (void)
46 {
47 #ifdef CONFIG_MMC
48         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49
50         setbits_be32(&gur->pmuxcr,
51                         (MPC85xx_PMUXCR_SD_DATA |
52                          MPC85xx_PMUXCR_SDHC_CD |
53                          MPC85xx_PMUXCR_SDHC_WP));
54
55 #endif
56         return 0;
57 }
58
59 int checkboard (void)
60 {
61         u8 vboot;
62         u8 *pixis_base = (u8 *)PIXIS_BASE;
63
64         puts("Board: MPC8536DS ");
65 #ifdef CONFIG_PHYS_64BIT
66         puts("(36-bit addrmap) ");
67 #endif
68
69         printf ("Sys ID: 0x%02x, "
70                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
71                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
72                 in_8(pixis_base + PIXIS_PVER));
73
74         vboot = in_8(pixis_base + PIXIS_VBOOT);
75         switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
76                 case PIXIS_VBOOT_LBMAP_NOR0:
77                         puts ("vBank: 0\n");
78                         break;
79                 case PIXIS_VBOOT_LBMAP_NOR1:
80                         puts ("vBank: 1\n");
81                         break;
82                 case PIXIS_VBOOT_LBMAP_NOR2:
83                         puts ("vBank: 2\n");
84                         break;
85                 case PIXIS_VBOOT_LBMAP_NOR3:
86                         puts ("vBank: 3\n");
87                         break;
88                 case PIXIS_VBOOT_LBMAP_PJET:
89                         puts ("Promjet\n");
90                         break;
91                 case PIXIS_VBOOT_LBMAP_NAND:
92                         puts ("NAND\n");
93                         break;
94         }
95
96         return 0;
97 }
98
99 #if !defined(CONFIG_SPD_EEPROM)
100 /*
101  * Fixed sdram init -- doesn't use serial presence detect.
102  */
103
104 phys_size_t fixed_sdram (void)
105 {
106         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
107         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
108         uint d_init;
109
110         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
111         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
112
113         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
114         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
115         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
116         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
117         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
118         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
119         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
120         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
121         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
122         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
123
124 #if defined (CONFIG_DDR_ECC)
125         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
126         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
127         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
128 #endif
129         asm("sync;isync");
130
131         udelay(500);
132
133         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
134
135 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
136         d_init = 1;
137         debug("DDR - 1st controller: memory initializing\n");
138         /*
139          * Poll until memory is initialized.
140          * 512 Meg at 400 might hit this 200 times or so.
141          */
142         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
143                 udelay(1000);
144         }
145         debug("DDR: memory initialized\n\n");
146         asm("sync; isync");
147         udelay(500);
148 #endif
149
150         return 512 * 1024 * 1024;
151 }
152
153 #endif
154
155 #ifdef CONFIG_PCI1
156 static struct pci_controller pci1_hose;
157 #endif
158
159 #ifdef CONFIG_PCIE1
160 static struct pci_controller pcie1_hose;
161 #endif
162
163 #ifdef CONFIG_PCIE2
164 static struct pci_controller pcie2_hose;
165 #endif
166
167 #ifdef CONFIG_PCIE3
168 static struct pci_controller pcie3_hose;
169 #endif
170
171 #ifdef CONFIG_PCI
172 void pci_init_board(void)
173 {
174         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
175         struct fsl_pci_info pci_info[4];
176         u32 devdisr, pordevsr, io_sel;
177         u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
178         int first_free_busno = 0;
179         int num = 0;
180
181         int pcie_ep, pcie_configured;
182
183         devdisr = in_be32(&gur->devdisr);
184         pordevsr = in_be32(&gur->pordevsr);
185         porpllsr = in_be32(&gur->porpllsr);
186         io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
187
188         debug("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
189
190         puts("\n");
191 #ifdef CONFIG_PCIE3
192         pcie_configured = is_serdes_configured(PCIE3);
193
194         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
195                 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
196                                 LAW_TRGT_IF_PCIE_3);
197                 set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
198                                 LAW_TRGT_IF_PCIE_3);
199                 SET_STD_PCIE_INFO(pci_info[num], 3);
200                 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
201                 printf("PCIE3: connected to Slot3 as %s (base address %lx)\n",
202                         pcie_ep ? "Endpoint" : "Root Complex",
203                         pci_info[num].regs);
204                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
205                                         &pcie3_hose, first_free_busno);
206         } else {
207                 printf("PCIE3: disabled\n");
208         }
209
210         puts("\n");
211 #else
212         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
213 #endif
214
215 #ifdef CONFIG_PCIE1
216         pcie_configured = is_serdes_configured(PCIE1);
217
218         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
219                 set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
220                                 LAW_TRGT_IF_PCIE_1);
221                 set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
222                                 LAW_TRGT_IF_PCIE_1);
223                 SET_STD_PCIE_INFO(pci_info[num], 1);
224                 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
225                 printf("PCIE1: connected to Slot1 as %s (base address %lx)\n",
226                         pcie_ep ? "Endpoint" : "Root Complex",
227                         pci_info[num].regs);
228                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
229                                         &pcie1_hose, first_free_busno);
230         } else {
231                 printf("PCIE1: disabled\n");
232         }
233
234         puts("\n");
235 #else
236         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
237 #endif
238
239 #ifdef CONFIG_PCIE2
240         pcie_configured = is_serdes_configured(PCIE2);
241
242         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
243                 set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
244                                 LAW_TRGT_IF_PCIE_2);
245                 set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
246                                 LAW_TRGT_IF_PCIE_2);
247                 SET_STD_PCIE_INFO(pci_info[num], 2);
248                 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
249                 printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n",
250                         pcie_ep ? "Endpoint" : "Root Complex",
251                         pci_info[num].regs);
252                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
253                                         &pcie2_hose, first_free_busno);
254         } else {
255                 printf("PCIE2: disabled\n");
256         }
257
258         puts("\n");
259 #else
260         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
261 #endif
262
263 #ifdef CONFIG_PCI1
264         pci_speed = 66666000;
265         pci_32 = 1;
266         pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
267         pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
268
269         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
270                 set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
271                                 LAW_TRGT_IF_PCI);
272                 set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
273                                 LAW_TRGT_IF_PCI);
274                 SET_STD_PCI_INFO(pci_info[num], 1);
275                 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
276                 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
277                         (pci_32) ? 32 : 64,
278                         (pci_speed == 33333000) ? "33" :
279                         (pci_speed == 66666000) ? "66" : "unknown",
280                         pci_clk_sel ? "sync" : "async",
281                         pci_agent ? "agent" : "host",
282                         pci_arb ? "arbiter" : "external-arbiter",
283                         pci_info[num].regs);
284
285                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
286                                         &pci1_hose, first_free_busno);
287         } else {
288                 printf("PCI: disabled\n");
289         }
290
291         puts("\n");
292 #else
293         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
294 #endif
295 }
296 #endif
297
298 int board_early_init_r(void)
299 {
300         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
301         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
302
303         /*
304          * Remap Boot flash + PROMJET region to caching-inhibited
305          * so that flash can be erased properly.
306          */
307
308         /* Flush d-cache and invalidate i-cache of any FLASH data */
309         flush_dcache();
310         invalidate_icache();
311
312         /* invalidate existing TLB entry for flash + promjet */
313         disable_tlb(flash_esel);
314
315         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
316                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
317                 0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
318
319         return 0;
320 }
321
322 int board_eth_init(bd_t *bis)
323 {
324 #ifdef CONFIG_TSEC_ENET
325         struct tsec_info_struct tsec_info[2];
326         int num = 0;
327
328 #ifdef CONFIG_TSEC1
329         SET_STD_TSEC_INFO(tsec_info[num], 1);
330         if (is_serdes_configured(SGMII_TSEC1)) {
331                 puts("eTSEC1 is in sgmii mode.\n");
332                 tsec_info[num].phyaddr = 0;
333                 tsec_info[num].flags |= TSEC_SGMII;
334         }
335         num++;
336 #endif
337 #ifdef CONFIG_TSEC3
338         SET_STD_TSEC_INFO(tsec_info[num], 3);
339         if (is_serdes_configured(SGMII_TSEC3)) {
340                 puts("eTSEC3 is in sgmii mode.\n");
341                 tsec_info[num].phyaddr = 1;
342                 tsec_info[num].flags |= TSEC_SGMII;
343         }
344         num++;
345 #endif
346
347         if (!num) {
348                 printf("No TSECs initialized\n");
349                 return 0;
350         }
351
352 #ifdef CONFIG_FSL_SGMII_RISER
353         if (is_serdes_configured(SGMII_TSEC1) ||
354             is_serdes_configured(SGMII_TSEC3)) {
355                 fsl_sgmii_riser_init(tsec_info, num);
356         }
357 #endif
358
359         tsec_eth_init(bis, tsec_info, num);
360 #endif
361         return pci_eth_init(bis);
362 }
363
364 #if defined(CONFIG_OF_BOARD_SETUP)
365 void ft_board_setup(void *blob, bd_t *bd)
366 {
367         ft_cpu_setup(blob, bd);
368
369         FT_FSL_PCI_SETUP;
370
371 #ifdef CONFIG_FSL_SGMII_RISER
372         fsl_sgmii_riser_fdt_fixup(blob);
373 #endif
374 }
375 #endif