board/freescale/mpc837xerdb/mpc837xerdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <env.h>
  10 #include <hwconfig.h>
  11 #include <i2c.h>
  12 #include <init.h>
  13 #include <asm/bitops.h>
  14 #include <asm/io.h>
  15 #include <asm/fsl_mpc83xx_serdes.h>
  16 #include <fdt_support.h>
  17 #include <spd_sdram.h>
  18 #include <vsc7385.h>
  19 #include <fsl_esdhc.h>
  20 #include <linux/delay.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #if defined(CONFIG_SYS_DRAM_TEST)
  25 int
  26 testdram(void)
  27 {
  28         uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  29         uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  30         uint *p;
  31
  32         printf("Testing DRAM from 0x%08x to 0x%08x\n",
  33                CONFIG_SYS_MEMTEST_START,
  34                CONFIG_SYS_MEMTEST_END);
  35
  36         printf("DRAM test phase 1:\n");
  37         for (p = pstart; p < pend; p++)
  38                 *p = 0xaaaaaaaa;
  39
  40         for (p = pstart; p < pend; p++) {
  41                 if (*p != 0xaaaaaaaa) {
  42                         printf("DRAM test fails at: %08x\n", (uint) p);
  43                         return 1;
  44                 }
  45         }
  46
  47         printf("DRAM test phase 2:\n");
  48         for (p = pstart; p < pend; p++)
  49                 *p = 0x55555555;
  50
  51         for (p = pstart; p < pend; p++) {
  52                 if (*p != 0x55555555) {
  53                         printf("DRAM test fails at: %08x\n", (uint) p);
  54                         return 1;
  55                 }
  56         }
  57
  58         printf("DRAM test passed.\n");
  59         return 0;
  60 }
  61 #endif
  62
  63 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  64 void ddr_enable_ecc(unsigned int dram_size);
  65 #endif
  66 int fixed_sdram(void);
  67
  68 int dram_init(void)
  69 {
  70         immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  71         u32 msize = 0;
  72
  73         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  74                 return -ENXIO;
  75
  76 #if defined(CONFIG_SPD_EEPROM)
  77         msize = spd_sdram();
  78 #else
  79         msize = fixed_sdram();
  80 #endif
  81
  82 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  83         /* Initialize DDR ECC byte */
  84         ddr_enable_ecc(msize * 1024 * 1024);
  85 #endif
  86         /* return total bus DDR size(bytes) */
  87         gd->ram_size = msize * 1024 * 1024;
  88
  89         return 0;
  90 }
  91
  92 #if !defined(CONFIG_SPD_EEPROM)
  93 /*************************************************************************
  94  *  fixed sdram init -- doesn't use serial presence detect.
  95  ************************************************************************/
  96 int fixed_sdram(void)
  97 {
  98         immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  99         u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 100         u32 msize_log2 = __ilog2(msize);
 101
 102         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 103         im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 104
 105         im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 106         udelay(50000);
 107
 108         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
 109         udelay(1000);
 110
 111         im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
 112         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 113         udelay(1000);
 114
 115         im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 116         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 117         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 118         im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 119         im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 120         im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
 121         im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 122         im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 123         im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 124         sync();
 125         udelay(1000);
 126
 127         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 128         udelay(2000);
 129         return CONFIG_SYS_DDR_SIZE;
 130 }
 131 #endif  /*!CONFIG_SYS_SPD_EEPROM */
 132
 133 int checkboard(void)
 134 {
 135         puts("Board: Freescale MPC837xERDB\n");
 136         return 0;
 137 }
 138
 139 int board_early_init_f(void)
 140 {
 141 #ifdef CONFIG_FSL_SERDES
 142         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 143         u32 spridr = in_be32(&immr->sysconf.spridr);
 144
 145         /* we check only part num, and don't look for CPU revisions */
 146         switch (PARTID_NO_E(spridr)) {
 147         case SPR_8377:
 148                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 149                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 150                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 151                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 152                 break;
 153         case SPR_8378:
 154                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 155                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 156                 break;
 157         case SPR_8379:
 158                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 159                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 160                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
 161                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 162                 break;
 163         default:
 164                 printf("serdes not configured: unknown CPU part number: "
 165                        "%04x\n", spridr >> 16);
 166                 break;
 167         }
 168 #endif /* CONFIG_FSL_SERDES */
 169         return 0;
 170 }
 171
 172 #ifdef CONFIG_FSL_ESDHC
 173 int board_mmc_init(bd_t *bd)
 174 {
 175         struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
 176         char buffer[HWCONFIG_BUFFER_SIZE] = {0};
 177         int esdhc_hwconfig_enabled = 0;
 178
 179         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
 180                 esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
 181
 182         if (esdhc_hwconfig_enabled == 0)
 183                 return 0;
 184
 185         clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
 186         clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
 187
 188         return fsl_esdhc_mmc_init(bd);
 189 }
 190 #endif
 191
 192 /*
 193  * Miscellaneous late-boot configurations
 194  *
 195  * If a VSC7385 microcode image is present, then upload it.
 196 */
 197 int misc_init_r(void)
 198 {
 199         int rc = 0;
 200
 201 #ifdef CONFIG_VSC7385_IMAGE
 202         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 203                 CONFIG_VSC7385_IMAGE_SIZE)) {
 204                 puts("Failure uploading VSC7385 microcode.\n");
 205                 rc = 1;
 206         }
 207 #endif
 208
 209         return rc;
 210 }
 211
 212 #if defined(CONFIG_OF_BOARD_SETUP)
 213
 214 int ft_board_setup(void *blob, bd_t *bd)
 215 {
 216 #ifdef CONFIG_PCI
 217         ft_pci_setup(blob, bd);
 218 #endif
 219         ft_cpu_setup(blob, bd);
 220         fsl_fdt_fixup_dr_usb(blob, bd);
 221         fdt_fixup_esdhc(blob, bd);
 222
 223         return 0;
 224 }
 225 #endif /* CONFIG_OF_BOARD_SETUP */