board/freescale/mpc837xerdb/mpc837xerdb.c

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  * Kevin Lam <kevin.lam@freescale.com>
   4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <hwconfig.h>
  11 #include <i2c.h>
  12 #include <asm/io.h>
  13 #include <asm/fsl_mpc83xx_serdes.h>
  14 #include <fdt_support.h>
  15 #include <spd_sdram.h>
  16 #include <vsc7385.h>
  17 #include <fsl_esdhc.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #if defined(CONFIG_SYS_DRAM_TEST)
  22 int
  23 testdram(void)
  24 {
  25         uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  26         uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  27         uint *p;
  28
  29         printf("Testing DRAM from 0x%08x to 0x%08x\n",
  30                CONFIG_SYS_MEMTEST_START,
  31                CONFIG_SYS_MEMTEST_END);
  32
  33         printf("DRAM test phase 1:\n");
  34         for (p = pstart; p < pend; p++)
  35                 *p = 0xaaaaaaaa;
  36
  37         for (p = pstart; p < pend; p++) {
  38                 if (*p != 0xaaaaaaaa) {
  39                         printf("DRAM test fails at: %08x\n", (uint) p);
  40                         return 1;
  41                 }
  42         }
  43
  44         printf("DRAM test phase 2:\n");
  45         for (p = pstart; p < pend; p++)
  46                 *p = 0x55555555;
  47
  48         for (p = pstart; p < pend; p++) {
  49                 if (*p != 0x55555555) {
  50                         printf("DRAM test fails at: %08x\n", (uint) p);
  51                         return 1;
  52                 }
  53         }
  54
  55         printf("DRAM test passed.\n");
  56         return 0;
  57 }
  58 #endif
  59
  60 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  61 void ddr_enable_ecc(unsigned int dram_size);
  62 #endif
  63 int fixed_sdram(void);
  64
  65 int dram_init(void)
  66 {
  67         immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  68         u32 msize = 0;
  69
  70         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  71                 return -ENXIO;
  72
  73 #if defined(CONFIG_SPD_EEPROM)
  74         msize = spd_sdram();
  75 #else
  76         msize = fixed_sdram();
  77 #endif
  78
  79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  80         /* Initialize DDR ECC byte */
  81         ddr_enable_ecc(msize * 1024 * 1024);
  82 #endif
  83         /* return total bus DDR size(bytes) */
  84         gd->ram_size = msize * 1024 * 1024;
  85
  86         return 0;
  87 }
  88
  89 #if !defined(CONFIG_SPD_EEPROM)
  90 /*************************************************************************
  91  *  fixed sdram init -- doesn't use serial presence detect.
  92  ************************************************************************/
  93 int fixed_sdram(void)
  94 {
  95         immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  96         u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  97         u32 msize_log2 = __ilog2(msize);
  98
  99         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 100         im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 101
 102         im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 103         udelay(50000);
 104
 105         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
 106         udelay(1000);
 107
 108         im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
 109         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 110         udelay(1000);
 111
 112         im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 113         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 114         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 115         im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 116         im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 117         im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
 118         im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 119         im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 120         im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 121         sync();
 122         udelay(1000);
 123
 124         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 125         udelay(2000);
 126         return CONFIG_SYS_DDR_SIZE;
 127 }
 128 #endif  /*!CONFIG_SYS_SPD_EEPROM */
 129
 130 int checkboard(void)
 131 {
 132         puts("Board: Freescale MPC837xERDB\n");
 133         return 0;
 134 }
 135
 136 int board_early_init_f(void)
 137 {
 138 #ifdef CONFIG_FSL_SERDES
 139         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 140         u32 spridr = in_be32(&immr->sysconf.spridr);
 141
 142         /* we check only part num, and don't look for CPU revisions */
 143         switch (PARTID_NO_E(spridr)) {
 144         case SPR_8377:
 145                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 146                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 147                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 148                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 149                 break;
 150         case SPR_8378:
 151                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 152                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 153                 break;
 154         case SPR_8379:
 155                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 156                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 157                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
 158                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 159                 break;
 160         default:
 161                 printf("serdes not configured: unknown CPU part number: "
 162                        "%04x\n", spridr >> 16);
 163                 break;
 164         }
 165 #endif /* CONFIG_FSL_SERDES */
 166         return 0;
 167 }
 168
 169 #ifdef CONFIG_FSL_ESDHC
 170 int board_mmc_init(bd_t *bd)
 171 {
 172         struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
 173         char buffer[HWCONFIG_BUFFER_SIZE] = {0};
 174         int esdhc_hwconfig_enabled = 0;
 175
 176         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 177                 esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
 178
 179         if (esdhc_hwconfig_enabled == 0)
 180                 return 0;
 181
 182         clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
 183         clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
 184
 185         return fsl_esdhc_mmc_init(bd);
 186 }
 187 #endif
 188
 189 /*
 190  * Miscellaneous late-boot configurations
 191  *
 192  * If a VSC7385 microcode image is present, then upload it.
 193 */
 194 int misc_init_r(void)
 195 {
 196         int rc = 0;
 197
 198 #ifdef CONFIG_VSC7385_IMAGE
 199         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 200                 CONFIG_VSC7385_IMAGE_SIZE)) {
 201                 puts("Failure uploading VSC7385 microcode.\n");
 202                 rc = 1;
 203         }
 204 #endif
 205
 206         return rc;
 207 }
 208
 209 #if defined(CONFIG_OF_BOARD_SETUP)
 210
 211 int ft_board_setup(void *blob, bd_t *bd)
 212 {
 213 #ifdef CONFIG_PCI
 214         ft_pci_setup(blob, bd);
 215 #endif
 216         ft_cpu_setup(blob, bd);
 217         fsl_fdt_fixup_dr_usb(blob, bd);
 218         fdt_fixup_esdhc(blob, bd);
 219
 220         return 0;
 221 }
 222 #endif /* CONFIG_OF_BOARD_SETUP */