2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/global_data.h>
30 #include <asm/mpc8349_pci.h>
32 #if defined(CONFIG_OF_FLAT_TREE)
34 #elif defined(CONFIG_OF_LIBFDT)
38 DECLARE_GLOBAL_DATA_PTR;
40 /* System RAM mapped to PCI space */
41 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
42 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
44 #ifndef CONFIG_PCI_PNP
45 static struct pci_config_table pci_mpc8349itx_config_table[] = {
53 pci_cfgfunc_config_device,
57 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
63 static struct pci_controller pci_hose[] = {
65 #ifndef CONFIG_PCI_PNP
66 config_table:pci_mpc8349itx_config_table,
70 #ifndef CONFIG_PCI_PNP
71 config_table:pci_mpc8349itx_config_table,
76 /**************************************************************************
79 * NOTICE: PCI2 is not currently supported
82 void pci_init_board(void)
84 volatile immap_t *immr;
85 volatile clk83xx_t *clk;
86 volatile law83xx_t *pci_law;
87 volatile pot83xx_t *pci_pot;
88 volatile pcictrl83xx_t *pci_ctrl;
89 volatile pciconf83xx_t *pci_conf;
94 struct pci_controller *hose;
96 immr = (immap_t *) CFG_IMMR;
97 clk = (clk83xx_t *) & immr->clk;
98 pci_law = immr->sysconf.pcilaw;
99 pci_pot = immr->ios.pot;
100 pci_ctrl = immr->pci_ctrl;
101 pci_conf = immr->pci_conf;
106 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
112 #ifdef CONFIG_HARD_I2C
114 /* Read the PCI_M66EN jumper setting */
115 if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
116 (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
117 if (reg8 & I2C_8574_PCI66)
118 clk->occr = 0xff000000; /* 66 MHz PCI */
120 clk->occr = 0xff600001; /* 33 MHz PCI */
122 clk->occr = 0xff600001; /* 33 MHz PCI */
125 clk->occr = 0xff000000; /* 66 MHz PCI */
131 * Release PCI RST Output signal
137 #ifdef CONFIG_MPC83XX_PCI2
143 /* We need to wait at least a 1sec based on PCI specs */
147 for (i = 0; i < 1000; i++)
152 * Configure PCI Local Access Windows
154 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
155 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
157 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
158 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
161 * Configure PCI Outbound Translation Windows
164 /* PCI1 mem space - prefetch */
165 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
166 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
167 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;
170 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
171 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
172 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
174 /* PCI1 mmio - non-prefetch mem space */
175 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
176 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
177 pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
180 * Configure PCI Inbound Translation Windows
183 /* we need RAM mapped to PCI space for the devices to
184 * access main memory */
185 pci_ctrl[0].pitar1 = 0x0;
186 pci_ctrl[0].pibar1 = 0x0;
187 pci_ctrl[0].piebar1 = 0x0;
188 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
189 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
191 hose->first_busno = 0;
192 hose->last_busno = 0xff;
194 /* PCI memory prefetch space */
195 pci_set_region(hose->regions + 0,
198 CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
200 /* PCI memory space */
201 pci_set_region(hose->regions + 1,
203 CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);
206 pci_set_region(hose->regions + 2,
208 CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
210 /* System memory space */
211 pci_set_region(hose->regions + 3,
212 CONFIG_PCI_SYS_MEM_BUS,
213 CONFIG_PCI_SYS_MEM_PHYS,
214 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
216 hose->region_count = 4;
218 pci_setup_indirect(hose,
219 (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
221 pci_register_hose(hose);
224 * Write to Command register
227 dev = PCI_BDF(hose->first_busno, 0, 0);
228 pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
229 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
230 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
233 * Clear non-reserved bits in status register.
235 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
236 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
237 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
239 #ifdef CONFIG_PCI_SCAN_SHOW
240 printf("PCI: Bus Dev VenId DevId Class Int\n");
245 hose->last_busno = pci_hose_scan(hose);
247 #ifdef CONFIG_MPC83XX_PCI2
251 * Configure PCI Outbound Translation Windows
254 /* PCI2 mem space - prefetch */
255 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
256 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
257 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;
260 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
261 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
262 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;
264 /* PCI2 mmio - non-prefetch mem space */
265 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
266 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
267 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;
270 * Configure PCI Inbound Translation Windows
273 /* we need RAM mapped to PCI space for the devices to
274 * access main memory */
275 pci_ctrl[1].pitar1 = 0x0;
276 pci_ctrl[1].pibar1 = 0x0;
277 pci_ctrl[1].piebar1 = 0x0;
279 PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
280 (__ilog2(gd->ram_size) - 1);
282 hose->first_busno = pci_hose[0].last_busno + 1;
283 hose->last_busno = 0xff;
285 /* PCI memory prefetch space */
286 pci_set_region(hose->regions + 0,
289 CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
291 /* PCI memory space */
292 pci_set_region(hose->regions + 1,
294 CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);
297 pci_set_region(hose->regions + 2,
299 CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);
301 /* System memory space */
302 pci_set_region(hose->regions + 3,
303 CONFIG_PCI_SYS_MEM_BUS,
304 CONFIG_PCI_SYS_MEM_PHYS,
305 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
307 hose->region_count = 4;
309 pci_setup_indirect(hose,
310 (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384));
312 pci_register_hose(hose);
315 * Write to Command register
318 dev = PCI_BDF(hose->first_busno, 0, 0);
319 pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
320 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
321 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
324 * Clear non-reserved bits in status register.
326 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
327 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
328 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
333 hose->last_busno = pci_hose_scan(hose);
337 #if defined(CONFIG_OF_LIBFDT)
339 ft_pci_setup(void *blob, bd_t *bd)
345 nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
346 if (nodeoffset >= 0) {
347 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
348 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
349 err = fdt_setprop(blob, nodeoffset, "bus-range",
352 tmp[0] = cpu_to_be32(gd->pci_clk);
353 err = fdt_setprop(blob, nodeoffset, "clock-frequency",
354 tmp, sizeof(tmp[0]));
356 #ifdef CONFIG_MPC83XX_PCI2
357 nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
358 if (nodeoffset >= 0) {
359 tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
360 tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
361 err = fdt_setprop(blob, nodeoffset, "bus-range",
364 tmp[0] = cpu_to_be32(gd->pci_clk);
365 err = fdt_setprop(blob, nodeoffset, "clock-frequency",
366 tmp, sizeof(tmp[0]));
370 #elif defined(CONFIG_OF_FLAT_TREE)
372 ft_pci_setup(void *blob, bd_t *bd)
377 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
379 p[0] = pci_hose[0].first_busno;
380 p[1] = pci_hose[0].last_busno;
383 #ifdef CONFIG_MPC83XX_PCI2
384 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
386 p[0] = pci_hose[1].first_busno;
387 p[1] = pci_hose[1].last_busno;
391 #endif /* CONFIG_OF_FLAT_TREE */
392 #endif /* CONFIG_PCI */